JPS6319628A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce a DC voltage component by making a voltage waveform impressed to a signal line asymmetrical about the potential of a substrate where a transparent conductor film is formed. CONSTITUTION:There is capacity Cgs between the gate, and source and drain of an MIS type FET. The DC voltage component between upon the Cgs is reduced by making the signal voltage waveform asymmetrical about the potential of a counter electrode. Namely, the signal voltage waveform generally varies between + or -VD about the potential VC of the counter electrode, but signal voltage waveforms are so set to VC+VD1 and VC-VD2, where VD1>0, VD2>0, and VD1>VD2. Those driving voltage waveforms are obtained by setting a signal waveform applied to a liquid crystal layer asymmetrically in advance and operate in such a direction that a drop in the potential at a contact L due to the influence of the Cgs is relaxed. Consequently, the DC voltage component applied to liquid crystal is reducible a liquid crystal display device which has high performance and high reliability is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for driving an active matrix type liquid crystal display device, and is particularly suitable for an intermediate display and for improving reliability. This invention relates to a method for driving a device.

[Conventional technology]

The active matrix method is being actively researched to improve the definition of liquid crystal display devices.6 FIG. 2 shows an equivalent circuit of the active matrix method. An FET 3 is arranged as an active element at each intersection of a plurality of row wirings 1 (referred to as scanning lines) and a plurality of column wirings 2 (referred to as signal lines) that are orthogonal to each other, and
One of the source and drain of the ET3 is connected to the signal line 2, the other to the liquid crystal 4, and the gate electrode to the scanning line 1. The liquid crystal 4 is sandwiched between the FET 3 and a substrate on which a transparent conductive film (referred to as a counter electrode) is formed on the entire surface facing the substrate on which the wiring is formed, and forms an electrical capacitor. The counter electrode is kept at a constant potential.

Normally, an alternating current voltage is applied to the signal line with the same amplitude and the polarity is reversed with respect to the counter electrode every cycle, and when the effective value of this alternating current signal applied to the liquid crystal exceeds a certain threshold, the liquid crystal becomes oriented. and - allows light in the polarization direction to pass through. The FET3 is a so-called TFT (Thin Fil+
m Transistor ) is used.

Explain dynamism. In the conventional driving method, the applied voltage relationship is as shown in the figure. When a positive voltage is applied to the gate, T
PT3 is turned on, a drain current flows, charge is injected into the capacitor 4 of the liquid crystal, and the potential VLC at the contact point eventually becomes equal to the data Vo.

(If the on-current of the TPT is low, the potential of L will not reach Vo during the time ts during which a positive voltage is applied to the gate. At this time, the positive and negative waveforms will not be symmetrical and a DC voltage component will be applied to the liquid crystal. ) Next, the gate potential becomes O or negative, TPT is turned off, and the charge accumulated in the liquid crystal is transferred to the liquid crystal's resistance RLC, capacitance CLC, and TPT's off resistance ROFF.
It is gradually discharged with a time constant determined by . Usually, the design is made to increase this time constant. After selecting other pixels,
- After a period, the gate voltage becomes positive again and TPT
is turned on. This time, a potential of -vD is applied to the signal line,
Charge is added to the signal line from the contact, the charge is discharged from the contact to the signal line, and soon the potential of the contact also becomes -Vo. When the gate voltage becomes negative or 0, this potential gradually attenuates as before, and as a result, a voltage that is alternately reversed between positive and negative is applied to the liquid crystal as shown in FIG.

Further, if the data is Ov, Ov is also applied to the liquid crystal.

As a modification of this, as shown in FIG. 4, a DC voltage Vc is applied to the opposite electrode of the liquid crystal, and the data is set to V.

There is also a method in which the VoO value is centered around +Vc, -Vo+Vc and Vc. (Ukai et al.
-Active matrix G using 3i thin film transistors
“Prototype production of HLCD” Institute of Electronics and Communication Engineers technical research report IE82-
69) [Problems to be Solved by the Invention] However, in general, a MIS type FET has a capacitance (referred to as Cgs) between the gate and the source/drain. This Cgs inevitably becomes large in a normal TPT structure called a staggered structure. Figure 5 shows staggered structure TPT.
FIG. 5 is an insulating substrate, 6 is a gate electrode, 7
, 8 are source/drain electrodes, 9 is a semiconductor layer, and 10 is a gate insulating film. There is an overlap between the gate and the source/drain.Generally, the width of this overlap is 1 to 2.
~10μm, and Cts is 0.05~0.
2 pF. On the other hand, the capacitance CLc of the liquid crystal connected to one pixel is 0.1 to 1 p, depending on the size of the pixel.
F, and Czs and CLc are at the same level. When such a large Cgs exists, a gate voltage pulse leaks into the voltage applied to the liquid crystal. (Ikeda et al.
"Liquid Crystal Display Using Thin Film Transistors" Technical Research Report CPM83-22, Institute of Electronics and Communication Engineers) This will be explained using FIG. 6. First, when a positive voltage pulse is applied to the gate, the potential at the contact becomes as high as C1B + CLC in accordance with the pulse height Vt. Since TPT is turned on, the potential of L increases from this potential as a starting point and settles at Vo as in the previous case. When the gate pulse falls, the potential at the contact point decreases by C, +CLC. After this, since TPT is in an off state, the potential is held. As in the previous case, CL, CIC□,
It is gradually discharged with a time constant determined by ROFF, CL (!).A similar thing occurs when the signal becomes -Vo after a - period.As a result, the voltage applied to the liquid crystal becomes as shown in Figure 6. The positive and negative asymmetry results, and a DC voltage component is always applied to the liquid crystal.If a DC voltage component is applied to the liquid crystal in this way, it causes alignment deterioration, which poses a problem in terms of service life.

An object of the present invention is to provide a driving method for reducing the DC voltage component caused by the above-mentioned CGS, and to realize a liquid crystal display device with high performance and high reliability.

[Means for solving the problem] The DC voltage component caused by Cgs as described above can be reduced by making the signal voltage waveform asymmetric with respect to the potential of the counter electrode. That is, generally the signal voltage waveform is equal to the potential V of the counter electrode.
Although the value of ±vD is taken with C as the center, the signal voltage waveform may instead be determined to satisfy the following conditions: V c +Vote Vc -Vo2, where vDl>O, Vow>O, and Vox>Vow.

By using this drive waveform, the above objective of reducing the DC voltage component applied to the liquid crystal layer can be achieved.

[Effect]

The above driving voltage waveform is a signal waveform applied to the liquid crystal layer that is set asymmetrically in advance, and acts in the direction of alleviating the drop in the potential of the contact due to the influence of Cts, so it is actually applied to the liquid crystal layer. The DC component of the applied voltage is reduced.

〔Example〕

The applied voltage is Ver Vol, Vc -Vow, V
oz＞O.

The relationship is Voz>Oy Voz>Voz.

If the time constant determined by Cts, CLC, RLC, and ROFF is longer than one cycle, the DC voltage component in the state of Vn = Voz is approximately given by Cts + CLO, so the value of Voz - Voz is Ct
s Cas + CLO The present invention provides Cgs + Ct,
c.

Vg, Vo, Vat, Vow, Vc (7
) Although not particularly limited to a specific value, for example, CLc=0
．． 2pF.

Cgs=0.04pF, -Vz=16V, Vc=7V.

When Voz = 8 V and Vnz = 5 V, the applied DC voltage component will be about -0.3 V,
The DC voltage component can be reduced to 115 or less compared to -1.7V when Vo=5V, which is a symmetrical signal waveform.

(Example 2).

In the first embodiment, the value of the voltage applied to the signal line corresponding to no signal is Vc, and the value of the opposing type Va is Vc.
With o as no signal state, the signal waveform is Vco + VDI,
VCO-Vo2e Vot> O+ Voz> O+V
By setting the value of the condition that a-work>Vow, -
It is possible to reduce the DC voltage component of the layer.

In addition, in the above Example 1 and Example 2, Voz)O#
VDt>0. It goes without saying that the magnitude of the necessary tear in the relationship VDt>Vow is not particularly limited; that is, the present invention is also effective for analog signal waveforms.

〔Effect of the invention〕

According to the present invention, the DC voltage component applied to the liquid crystal can be reduced without changing the structure of the liquid crystal display, and a liquid crystal display having high performance and high reliability can be obtained.

2 are planar equivalent circuits of a liquid crystal display device, FIGS. 3, 4, and 6 are diagrams for explaining conventional driving methods, and FIG. 5 is a cross-sectional view showing a conventional TPT. be.

1...Scanning line, 2...Signal line, 3...TFT, 4
···liquid crystal.

5... Insulating substrate, 6... Gate electrode, 7, 8...
・Sohn Vc f-β Fig. 1 CC) Ver>Vθ2nθ Not 1 (b) VC 21 Fig. 1 (d) V9+ >Voz >l), Vto > V
c te 2 fig.

Claims (1)

[Claims] 1. A substrate including a plurality of signal lines and a plurality of scanning lines orthogonal to the signal lines, with an active element formed near the intersection of both lines, and a substrate formed with a transparent conductor film, In a method for driving a liquid crystal display device in which the two substrates face each other with a liquid crystal interposed therebetween, and the active element is used to control the voltage applied to the liquid crystal, the voltage waveform applied to the signal line is controlled by the substrate on which the transparent conductor film is formed. 1. A method for driving a liquid crystal display device, characterized in that the potential is asymmetric with respect to the potential of the liquid crystal display device.