JPS63193060A - Receiving apparatus for ultrasonic flaw detection - Google Patents

Abstract

PURPOSE:To set an ultrasonic signal to the optimum level, by a method wherein the output of the containing the reflected wave of a flaw in a received ultrasonic signal is variably amplified to detect the peak value thereof and the gain of a variable amplifier is determined on the basis of the detected peak value. CONSTITUTION:The received ultrasonic signal A from a probe is amplified by a preamplifier 1 and a time gate signal is inputted to a time gate circuit 2 and a signal containing the reflected wave of a flaw is separated from other signal to pass only for a specific period. The output signal B of the circuit 2 is amplified by a variable amplifier 3 and the variably amplified output signal C is sent to a signal processing apparatus and a peak detection circuit 4. This circuit 4 detects the first peak value P wherein the peak value of the output signal C exceeds a threshold value. The detected peak value P is inputted to a gain determining circuit 5 and a new gain optimizing the output signal C is calculated from the present gain (order) and the detected peak value P to issue a command to the variable amplifier. Therefore, the adjustment work of an inspector is made unnecessary at the time of ultrasonic flaw detection and the optimum gas is automatically determined to make it possible to enhance flaw detection accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an ultrasonic flaw detection receiving device that amplifies a received ultrasonic signal of an ultrasonic flaw detection device.

[Conventional technology]

In conventional ultrasonic flaw detection equipment, the strength of the received ultrasonic signal is weak, and in order to obtain good reception strength, it is necessary to amplify the received signal with an ultrasonic receiving circuit. The optimal amplification factor of the receiving circuit during this ultrasonic flaw detection varies depending on the intensity of the transmitted ultrasonic waves, the characteristics of the receiving contact, the characteristics of the object, the ultrasonic reflection characteristics of the defect, etc. In conventional ultrasonic flaw detection, the inspector would adjust the gain of the amplifier prior to flaw detection in order to optimize the level of such received transsonant signals.

Furthermore, regarding the conventional AGC circuit that automatically controls the gain of the receiver according to the strength of the received continuous wave signal such as a general video signal and always outputs a signal at a constant level, please refer to the "R Television Image Engineering Handbook", for example. Edited by academic societies,
Discussed on pages 983 to 984, published by Ohmsha (1981).

[Problem that the invention seeks to solve]

In the above conventional technology, an inspector adjusts the gain of an amplifier prior to flaw detection in order to optimize the level of a received ultrasonic signal during ultrasonic flaw detection. Further, in the AGC circuit of a general receiver, the gain for amplifying the received signal is automatically determined, but the received signal is intended for a temporally continuous signal such as a television video signal.

On the other hand, the received ultrasonic signal is a pulse-like signal whose generation time and intensity are uncertain, and is not a continuous signal targeted by the AGC circuit.

Therefore, if a conventional AGC circuit is applied to the amplifier of the received ultrasonic signal, the AGC circuit determines that the gain is low during the period when there is no received signal and increases the gain, so that it is optimal when the received signal is input. There was a problem that it could not be applied because there was a fear that the amplification would not be achieved with a certain gain.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ultrasonic flaw detection receiver that can eliminate the need for gain adjustment by an inspector by automatically determining the gain for amplifying a pulsed received ultrasonic signal to an optimum level.

[Means for solving problems]

The above purpose is to provide an ultrasonic flaw detection device that uses ultrasonic waves to detect defects in a specimen, including a time gate circuit that allows a received ultrasonic signal to pass only for a predetermined period of time, and a variable amplifier that amplifies the output signal of the time gate circuit. and a peak value detection circuit for detecting a peak value of a signal whose amplitude exceeds a predetermined threshold value of the output signal of the variable amplifier, and determining the gain of the variable amplifier based on the peak value detected by the peak value detection circuit. This is achieved by an ultrasonic flaw detection receiving device comprising a gain determining circuit that issues commands.

[Effect]

In the ultrasonic flaw detection receiver described above, the part of the received ultrasonic signal that is reflected from a defect is output through a time gate circuit, and then amplified by a variable amplifier and output. A peak value detection circuit detects the peak value of a signal that does not contain noise that exceeds the above value, and a gain determination circuit uses that peak value to determine and command the optimum gain of the variable amplifier, thereby ensuring a good level at all times. The received signal of the reflected wave from the defect is changed.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 11.

FIG. 1 is a block diagram showing an embodiment of an ultrasonic flaw detection receiving device according to the present invention. In Fig. 1, 1 amplifies a received ultrasonic signal A obtained by a receiving probe of an ultrasonic flaw detection device that detects defects in an object using ultrasonic waves, with a predetermined constant gain. This is the front stage amplifier. 2 is a switch that allows the output signal of the preamplifier 1 to pass only during a specific period when a time gate signal set from the outside is input to separate the defective reflected wave signal of the received ultrasonic signal A from other signals and output it. This is a time gate circuit consisting of elements.

3 is a variable amplifier that amplifies the output signal B of the time gate circuit 2 with a gain that can be changed by an external command. 64 is a variable amplifier that inputs the output signal C of the variable amplifier 3 to a signal processing device for ultrasonic flaw detection. This is a peak value detection circuit that detects the peak value of the output signal C that exceeds a threshold value set from the outside for the first time during the period in which the time gate signal is input. Reference numeral 5 denotes a gain determining circuit that determines the gain to be commanded to the variable amplifier 3 based on the peak value detected by the peak value detecting circuit 4. Note that the same reference numerals or symbols indicate the same or corresponding parts throughout the drawings.

Figure 2 is a timing chart illustrating the signal waveform at each point in Figure 1.
This will be explained using figures. First, as shown in the signal waveform of the received ultrasonic signal A in FIG. 2, the transmitted ultrasonic wave (transmitted ultrasonic wave) in ultrasonic flaw detection is a single ultrasonic wave. On the other hand, reflected waves from defects in the object and reflected waves from the bottom surface (multiple echoes) obtained by the receiving probe exhibit signal waveforms of several periods.

The present invention utilizes this reflected wave characteristic. Received ultrasound signal A
is amplified with a constant gain by the preamplifier 1 and then input to the time gate circuit 2.The time gate signal that opens the 1-hour gate circuit 2 has its signal start time and signal period set externally by the user of the device. . In the signal waveform of the time gate signal in Fig. 2, the period of signal level ``H'' indicates the period in which the time gate signal is input. It is used to separate the ultrasonic wave and the reflected wave from the bottom surface, and the one-hour gate circuit 2 allows the received ultrasonic signal A to pass only during a specific period when the time gate signal is input to detect defects in the variable amplifier 3. An output signal B containing only reflected waves is input. The next variable amplifier 3, peak value detection circuit 4, and gain determining circuit 5 form a feedback loop that determines the gain of the variable amplifier 3 based on the amplitude of the output signal C of the variable amplifier 3. First, the output signal C amplified by the current gain of the variable amplifier 3 is output to the signal processing device for ultrasonic flaw detection and is also input to the peak value detection circuit 4. Then, the peak value detection circuit 4 operates only during the period when the time gate signal is input, and compares the amplitude of the output signal C of the variable amplifier 3 with a threshold value set from the outside by the user of the device.

When the output signal C with an amplitude larger than the threshold value is input, the peak value detection operation is started, and only the first peak value P is detected as shown in the signal waveform of the output signal C in Fig. 2. , even if a signal waveform larger than the peak value P is subsequently input, it is not detected and the first peak value P is transferred to the gain determining circuit 5 at the time of detection. Here, the gain determining circuit 5 calculates a new gain that should maximize the output signal C amplified by the variable amplifier 3 based on the current gain (command) output to the variable amplifier 3 and the peak value P. Output to variable amplifier 3. For example, assuming that the current gain is 01, the peak value is P, and the maximum output value of the variable amplifier 3 is P□8, a new gain G is calculated by the following equation and output.

G=GzX (P-ax/P) ”・(1
) In this way, the gain of the variable amplifier 3 changes from the current gain G1 to the new gain G as shown in the signal waveform of the output of the gain determining circuit 5, that is, the gain of the variable amplifier 3 in FIG. As shown in the signal waveform of the output signal C, the signal waveform that is continuously input from the time when the first peak value P of the output signal C is detected is amplified to the optimum level (maximum level) with the new gain G. According to the six examples to be output.

After separating the reflected waves due to defects from the received ultrasonic signal A by one ultrasonic transmission, the optimum gain of the amplifier is determined by detecting the peak value P of the signal waveform that first exceeds the threshold. The subsequent signal waveform can be amplified to an optimal level, and this output is sent to a signal processing device for ultrasonic flaw detection.

Next, FIG. 3 is a circuit diagram showing an embodiment of the variable amplifier 3 of FIG. 1. In FIG. 3, OPI.

OF2 is an operational amplifier, Rttt Rtxe Rtt-
RnteR12~RII! are resistances, Sxx to Sn1. S
zx to Sat are switches. With this configuration, the switch Sz corresponds to the gain (command) determined by the gain determining circuit 5.
The gain of variable amplifier 3 can be changed by opening and closing t~Snz and switches SSX~S1.

For example, depending on the gain (command), switches Sll, S12
The overall gain G of the operational amplifiers OPI and OP2 when G is closed and all other switches are open is given by the following equation.

G = (Rxt/ Rzx) X (Rxz/ Rtz
) (2) FIG. 4 is a circuit diagram showing an embodiment of the peak value detection circuit 4 shown in FIG. 1. In Figure 4, 4
a is an A/D converter, 4b to 4d are latch circuits (sample and hold circuits), 4e is an oscillator, 4f is a digital comparator, 4g is an analog comparator, 4h, 4
i is an AND circuit, 4j and 4 are inverters, and 4Q is a D flip-flop. FIG. 5 is a timing chart illustrating signal waveforms at each point in FIG. 4. Next, the operation of the configuration shown in FIG. 4 will be explained with reference to FIG. First, the output signal C of the variable amplifier 3 during the input period of the time gate signal shown in FIG. 5 is digitized by the A/D converter 4a in synchronization with the clock shown in FIG. Data is sequentially latched by the latch circuit 4b and output from the Q terminal of the latch circuit 4b to the next latch circuit 4c and digital comparator 4f. In addition, since the peak value of the output signal C is valid only when it is larger than the threshold value set externally, the analog comparator 4g compares the output signal C and the threshold value, and the output signal C is the threshold value. The peak detection operation is performed only when the value is larger than the maximum value. Therefore, as shown in FIG. 5, only when the output of the analog comparator 4g is at H level, a digital Comparator 4f
make it work. Here, the digital comparator 4f starts operating at time tl in FIG. 5, compares the values of its inputs A and B, and if A>H, the (A>B) terminal becomes H level, so the AND circuit The clock of the oscillator 4e is inputted to the CK terminal of the latch circuit 4c via 41 as shown in FIG. Then, as shown in FIG. 5, the latch circuit 4c latches the data input from the D terminal every time a clock is input and outputs it to the Q terminal. In this way, the latch circuit 4c
The data input to the D terminal of the latch circuit 4c is updated by digitizing the output signal C every clock of the oscillator 4e, so while the digital comparator 4f is operating, the data input to the Q terminal of the latch circuit 4c is updated at that point. The signal level value of is output. Then, at time t2 in Figure 5,
The values of inputs A and B of digital comparator 4 f are A
Since ≦B (A>B), one child becomes L level. Using this L level signal, the value of the final stage latch circuit 4d is updated via the inverter 4j as shown in FIG.
Output to. Here, the D flip-flop 4n has a function of detecting only the first peak value of the signal waveform as described above when the output signal C having a level higher than the threshold value as shown in FIG. 5 is input. In other words, the L level signal at the (A>B) terminal of the digital comparator 4f is inverted by the inverter 4, and the CLR (
Clear) terminal and sets the output of the Q terminal of the D flip-flop 4Ω to L level, thereby stopping the operation of the digital comparator 4f. Note that the signal at the (A>B) terminal of the digital comparator 4f is output to the gain determining circuit 5. According to this embodiment, the first peak value of the output signal C that is equal to or higher than the threshold value can be detected.

No malfunction occurs due to noise below the threshold.

FIG. 6 is a circuit diagram showing an embodiment of the gain determining circuit 5 of FIG. 1. In FIG. 6, this gain determining circuit 5 is a circuit that determines the optimum gain G based on the current gain G1 and a newly input peak value, and 5a is a D flip-flop;
b and 5c are NAND circuits, 5d and 5e are monostable vibrators, 5f is an OR circuit, 5g is a latch circuit, and 5h is a ROM for storing gain values. With this configuration of the D flip-flop 5a to OR circuit 5f, a latch signal to be input to the latch circuit 5g is generated using the one-hour gate signal and the signal generated when the peak value detection circuit 4 detects a peak value. The seventh time is a timing chart illustrating the operation waveform at each point when the peak value of FIG. 6 is input. First, the operation of the configuration shown in FIG. 6 will be explained with reference to FIG. Now, the current gain (command) G1 shown in FIG. 7 is output from the Q terminal of the latch circuit 5g to the variable amplifier 3, and the R
It is input to the address terminal AIS''A13 of OM5h.

Next, when the peak value detected by the peak value detection circuit 4 is input to the address terminals A1 to A4 of the ROM during the period when the time gate signal shown in FIG. The signal shown in FIG. 7 is input to the D flip-flop 5a, and the Q terminal of the D flip-flop 5a becomes H level. The terminal of this D flip-flop 5a is the address terminal A of the ROM 5h.

address terminal A at this point.

The data in the ROM 5h corresponding to the address of ~Aza is output to the latch circuit 5g. At this time, a latch signal is output from the OR circuit 5f to the latch circuit 5g, and the data is latched to the latch circuit 5g and output. In this way, the next gain G can be determined based on the current gain G1 and the newly input peak value and output to the variable amplifier 3. Furthermore, ROM5
Since the data stored in h is the current gain Gl at addresses A13 to A6 and the new peak value at addresses A4 to A1, the corresponding gain G is calculated in advance.

Next, FIG. 8 is a timing chart illustrating operation waveforms at each point when the peak value of FIG. 6 is not input.

Next, the operation of the configuration shown in FIG. 6 will be explained with reference to FIG. First, the address Ao is used to determine whether a peak value is detected for each time gate signal, and the address Ao is for determining whether a peak value is detected for each time gate signal.
If the peak value in the figure exists, it becomes H level, but the 8th
When the peak value shown in the figure does not exist, it becomes L level. This is because the received signal is not always changed during the period in which the time gate signal is input during ultrasonic flaw detection, and this is because there is no defect or the previous gain was too large. Therefore, when the peak value is not input as shown in FIG. 8, the gain is increased at the end of the time gate signal. That is, when the peak value is not detected and no signal is input, the D flip-flop 5a
The Q terminal of becomes L level. Therefore, the data stored in the ROM 5h is set to a constant value for the address A s = A t a regardless of the peak value of the address A 1 "A 4 at the address where the address Ao is at the L level.

The gain is output by a latch signal at the end of the time gate signal. Note that if the peak value continues to be undetected, the gain will continue to increase, but the gain is limited so as not to exceed a certain value to prevent unnecessary increases in the gain.

Next, FIG. 9 is a diagram showing the relationship between the output signal C of the received ultrasonic signal A and the threshold level, showing another embodiment of the peak value detection circuit 4 shown in FIG. In FIG. 9, in the above embodiment, a signal C which exceeds the threshold value P1 at the beginning of the signal waveform of several periods of the output signal C obtained by amplifying the received ultrasound signal A by the variable amplifier 3 is shown.
By detecting the peak value of the output signal C, the subsequent signal C can be amplified with an optimal gain. In this embodiment, the threshold level is set to the threshold P according to the level of the output signal C
I, P2. Each different peak value is measured at a different time point Pi by varying Ps.

P2. Ps can be detected and the subsequent signal C can be amplified with an optimal gain. FIG. 10 is a block diagram showing another embodiment of the ultrasonic flaw detection receiving apparatus according to the present invention. In FIG. 10, 6 is a delay circuit, and 7 is a variable amplifier. In this embodiment, the configuration is such that the entire signal waveform of the received ultrasonic signal B from the defect is amplified with a constant gain, and after the received ultrasonic signal B that has passed through the time gate circuit 2 is delayed by the delay circuit 6, The delayed received ultrasonic signal is amplified by the variable amplifier 7 with the optimum gain determined by the gain determining circuit 5 using the method described above. FIG. 11 is a timing chart illustrating signal waveforms at each point in FIG. 10. Next, the operation of the configuration shown in FIG. 10 will be explained with reference to FIG. 11. The defective received ultrasonic signal B, in which the received ultrasonic signal A has now passed through the time gate circuit 2, is amplified by the variable amplifier 3, and the output signal C of the variable amplifier 3 exceeds the threshold value for the first time in the peak value detection circuit 4. The peak value is detected, and the signal waveform from the next period is amplified with the gain determined by the gain determining circuit 5 based on this peak value. However, in this embodiment, the received ultrasonic signal B is delayed by the delay circuit 6. is amplified from the waveform of the first period by the variable amplifier 7 with the gain determined by the gain determining circuit 5, and outputs an output signal E in which all the signal waveforms of the received ultrasonic signal B are amplified with a constant gain. Note that the delay time of the delay circuit 6 is set in advance based on the frequency of the transmitted ultrasound and the number of cycles of the received ultrasound.

In this manner, according to the above embodiment, whereas in conventional ultrasonic flaw detection, the gain of the received ultrasonic amplifier was set once and then tested without changing it, the received ultrasonic Since the optimum gain of the sound waves can be calculated, if the optimum gain is determined for a certain period at the start of flaw detection and then amplified at a constant gain, the inspector will not have to adjust the gain every time the inspection conditions change during flaw detection. No longer needed.

〔Effect of the invention〕

According to the present invention, it is possible to automatically determine the optimum gain without the need for an inspector to adjust the gain of an amplifier, which was necessary for an inspector to optimize the level of received ultrasonic waves during conventional ultrasonic flaw detection. This reduces flaw detection work time, prevents defects from being overlooked due to poor gain settings, and improves work efficiency and accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an ultrasonic flaw detection receiver according to the present invention, FIG. 2 is a timing chart of FIG. 1, FIG. 3 is a circuit diagram of the variable amplifier of FIG. is a circuit diagram of the peak value detection circuit of FIG. 1, FIG. 5 is a timing chart of FIG. 4, FIG. 6 is a circuit diagram of the gain determining circuit of FIG. 1, and FIG. 7 is a circuit diagram of the peak value detection circuit of FIG. FIG. 8 is a timing chart when the peak value shown in FIG. 6 is not input. FIG. 9 is a diagram showing the relationship between the received ultrasonic signal and the threshold level of the peak value detection circuit shown in FIG. 1. , FIG. 10 is a block diagram showing another embodiment of the ultrasonic flaw detection receiving apparatus according to the present invention, and FIG. 11 is a timing chart of FIG. 10. 1... Pre-stage amplifier, 2... Time gate circuit, 3...
- Variable amplifier, 4... Peak value detection circuit, 5... Gain determining circuit, 6... Delay circuit, 7... Variable amplifier.

Claims (1)

[Claims] 1. In an ultrasonic flaw detection device that uses ultrasonic waves to detect defects in a specimen, the received ultrasonic signal is used to pass a portion of the received ultrasonic signal that includes a reflected wave from the defect. a time gate circuit that allows the signal to pass through for only a predetermined period; a variable amplifier that amplifies the output signal of the time gate circuit with a variable gain according to an external command and outputs the amplified signal; a peak value detection circuit that detects the peak value of the signal; and a gain determination circuit that determines the gain of the variable amplifier based on the peak value detected by the peak value detection circuit and issues an external command to the variable amplifier. Receiving device for ultrasonic flaw detection. 2. The receiving device for ultrasonic flaw detection according to claim 1, wherein said peak value detection circuit detects only the first peak value of a signal whose amplitude of said variable amplifier exceeds a predetermined threshold. 3. The gain determining circuit determines a new gain from the gain before the peak value was detected and the peak value detected during the predetermined period, and also determines a new gain when no peak value is detected during the predetermined period. 2. The receiving device for ultrasonic flaw detection according to claim 1, wherein the new gain is determined only from the previous gain.