JPS63192833U - - Google Patents
Info
- Publication number
- JPS63192833U JPS63192833U JP8285887U JP8285887U JPS63192833U JP S63192833 U JPS63192833 U JP S63192833U JP 8285887 U JP8285887 U JP 8285887U JP 8285887 U JP8285887 U JP 8285887U JP S63192833 U JPS63192833 U JP S63192833U
- Authority
- JP
- Japan
- Prior art keywords
- data
- function
- setting means
- memory
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006870 function Effects 0.000 claims description 9
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 230000006386 memory function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Or Calibration Of Command Recording Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Input From Keyboards Or The Like (AREA)
Description
第１図はこの考案の一実施例の全体を示すブロ
ツク線図、第２図はその入力装置と制御装置の構
成を示すブロツク線図である。
図面において、１は入力装置、２は出力データ
用メモリ、３は制御装置、４は負荷、５は出力装
置、１１はフアンクシヨンスイツチ、１２はデー
タ入力スイツチ、３１はＣＰＵ、３２はデータラ
ツチ回路、３３はコンパレータである。
FIG. 1 is a block diagram showing the entire embodiment of this invention, and FIG. 2 is a block diagram showing the configuration of the input device and control device. In the drawing, 1 is an input device, 2 is an output data memory, 3 is a control device, 4 is a load, 5 is an output device, 11 is a function switch, 12 is a data input switch, 31 is a CPU, and 32 is a data latch circuit. , 33 are comparators.
Claims (1)
ータとを設定する設定手段と、この設定手段から
の前記フアンクシヨンと前記設定数値とを記憶す
るメモリ手段とを備えたメモリ装置において、前
記設定手段からの前記フアンクシヨンデータと前
記設定数値データとを一時的に記憶し、前記フア
ンクシヨンデータが異なつて入力された場合は以
降の前記メモリへの前記データの書込みを禁止あ
るいは前記データの全てをクリアする制御回路を
備えていることを特徴とするメモリ装置のチエツ
ク装置。 (2) 実用新案登録請求の範囲第１項の記載にお
いて、前記制御回路は、前記設定手段からの前記
フアンクシヨンデータが入力され、その情報を一
時的に記憶するメモリ機能を備えた中央処理装置
と、前記設定手段から順次入力される前記設定数
値と前記中央処理装置に記憶された前記フアンク
シヨンとを比較し、前記フアンクシヨンが異なつ
た時は前記中央処理装置に記憶された前記フアン
クシヨンと前記設定数値の全てをクリアするよう
に前記中央処理装置に指示する比較回路とを備え
ていることを特徴とするメモリ装置のチエツク装
置。[Claims for Utility Model Registration] (1) A utility model comprising a setting means for setting arbitrary function data and set numerical value data, and a memory means for storing the function and the set numerical value from the setting means. In a memory device, the function data and the set numerical data from the setting means are temporarily stored, and when the function data are inputted differently, the data is subsequently written to the memory. A check device for a memory device, comprising a control circuit for inhibiting or clearing all of the data. (2) In the description of claim 1 of the utility model registration claim, the control circuit is a central processing unit that receives the function data from the setting means and has a memory function to temporarily store the information. The device compares the set numerical values sequentially inputted from the setting means with the function stored in the central processing unit, and when the functions are different, compares the function stored in the central processing unit with the setting. 1. A check device for a memory device, comprising: a comparison circuit for instructing the central processing unit to clear all numerical values.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8285887U JPH057637Y2 (en) | 1987-05-29 | 1987-05-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8285887U JPH057637Y2 (en) | 1987-05-29 | 1987-05-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63192833U true JPS63192833U (en) | 1988-12-12 |
| JPH057637Y2 JPH057637Y2 (en) | 1993-02-25 |
Family
ID=30935897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8285887U Expired - Lifetime JPH057637Y2 (en) | 1987-05-29 | 1987-05-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH057637Y2 (en) |
-
1987
- 1987-05-29 JP JP8285887U patent/JPH057637Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057637Y2 (en) | 1993-02-25 |
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