JPS63191426A - Selective call receiver - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to reduce its size by composing a voltage boosting circuit of a separately excited DC voltage converter, and supplying an internal clock generated by the clock generating circuit of a 1st control circuit as an operation clock to the voltage boosting circuit and a 2nd control circuit. CONSTITUTION:The voltage boosting circuit C is composed of the separately excited DC voltage converter and the internal clock generated by the clock generating circuit of the 1st control circuit A is supplied as the operation clock to the voltage boosting circuit C and the 2nd control circuit B. Consequently, any clock generating circuit need not be added to simplify the circuit constitution of a receiver and also reduce its size, and the internal clock is a stable clock used for synchronization, so a microprocessor and the voltage boosting circuit are always operated stably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an improvement in a selective call receiver having a message display function.

(Prior art) In general, a selective call receiver receives and demodulates a selective call signal sent from a base station in a radio circuit section, and stores the individual number code inserted in this signal in a memory in a code matching section. It is configured to check the individual number code of the own machine, and if the two codes match, output a ringing signal from the call control unit and generate a ring tone from the speaker, thereby notifying the occurrence of a call. . In an actual receiver, the code matching section and the call control section of each of the above circuit sections are constructed from a single control LSI consisting of a logic integrated circuit along with a bit synchronization circuit, a clock generation circuit, etc. We are trying to make it smaller.

On the other hand, recently, a new type of selective calling receiver and one having a function of displaying message information in addition to displaying a single call has been developed. When this type of receiver determines that a call has occurred to its own machine as a result of matching individual number codes, it generates a ring tone to notify that a call has occurred, and also generates a ring tone that is inserted into the selective call signal. The message information is decoded and the message is visually displayed on a liquid crystal display or the like. Here, as the message, for example, a contact telephone number is applied.

By the way, when configuring this receiver, it is necessary to decode message information and control its display in addition to code checking, etc., but the circuits that perform these operations are all implemented by a control LSI consisting of a logic integrated circuit. This is generally difficult to achieve.

Therefore, in the past, a control circuit consisting of a microprocessor was provided in addition to the control LSI, and this control circuit performed code verification, control of ring tone generation, decoding of message information, and control of its display. The control LSI is configured to perform synchronization and generation of an internal clock.

Since a microprocessor generally requires an N source voltage of 3V or more and cannot be operated with the receiver's battery voltage (1.5V), a booster circuit is provided and a circuit that generates a clock for the microprocessor's operation is provided. This was achieved by doing this.

However, such conventional receivers must be equipped with an operation clock generation circuit for the microprocessor, and if a separately excited DC-DC converter is used as the boost circuit, a clock generation circuit is also required for this converter. Therefore, there was a drawback that the configuration of the receiver became large. Additionally, if a self-excited DC-DC converter is used as the boost circuit, a clock generation circuit for the boost circuit can be eliminated; however, in general, self-excited DC-DC converters cause frequency changes in order to stabilize the output voltage. , there was a problem that the high frequency had a negative effect on the wireless line.

(Problems to be Solved by the Invention) As described above, the conventional receiver has a clock generation circuit in addition to the addition of a microprocessor and a booster circuit, so the configuration of the receiver becomes complicated and large. In view of this problem, the present invention makes it possible to supply a stable lock to the microprocessor and the promotion circuit without providing a new lock generation circuit, thereby simplifying the circuit configuration. Another object of the present invention is to provide a selective calling receiver with a message display function that can be miniaturized.

[Structure of the Invention] (Means for Solving the Problems) The present invention, as shown in FIG. a first control circuit A having a clock generation circuit; and a second control circuit comprising a microprocessor that performs verification of individual number codes and controls call display when the codes match, as well as deciphers and controls display of message information. B, and this second control circuit B
A booster circuit C that generates an operating voltage of mN from the battery voltage.
This step-up circuit C is constituted by a separately excited DC voltage converter, and this step-up circuit C and the second
The internal clock generated from the clock generation circuit of the first control circuit A is supplied to the control circuit B of the first control circuit A as an operating clock.

(Function) As a result, the clocks generated from the existing internal clock generation circuit provided in the first control circuit are supplied as operating clocks to the second control circuit B and the booster circuit C, each of which is made up of a microprocessor. Therefore, there is no need to provide an additional clock generation circuit, and the circuit configuration of the receiver can be simplified and downsized accordingly. Furthermore, since the internal clock is a stable lock used for synchronization, the microprocessor and booster circuit can always operate stably.

(Embodiment) FIG. 2 is a block diagram showing the circuit configuration of a selective call receiver in an embodiment of the present invention. This receiver receives a selective call signal arriving from a base station via an antenna 1 at a radio circuit 21, and then a demodulation circuit 22 receives a selective call signal from a base station. ! a first control circuit 3 consisting of a logic integrated circuit, a second control circuit 4 consisting of a microprocessor, and an '88'M voltage (Vccl = 1.5 V).
A booster circuit 6 is provided for supplying an operating power supply voltage (Vcc2-3.0 V) to the second control circuit 4.

Of these, the first control circuit 3 includes a clock generation circuit 32 that generates an internal clock of, for example, 32 ktlx using an external crystal oscillator 31 as a reference source, and an internal clock CLK generated from this clock generation circuit 32. The internal clock CL generated from the bit synchronization circuit 33 and the clock oscillation circuit 32 that synchronizes the selective call signal demodulated by the demodulation circuit 22 with the control pulse
It is comprised of a fundamental frequency generation circuit 34 which generates a ringing signal necessary for generating a ringing tone by frequency dividing K, and a clock control circuit 35. This clock control circuit 35 controls the battery voltage V when the power switch is turned off.
ccl, a gate section that gate-controls the supply of the clock CLK to the booster circuit 6, and a means for determining the operating state of the second control circuit 4. When the supply off of the voltage V ccl is detected, the determination means determines whether or not the second control circuit 4 needs to continue its operation, and if it is necessary to continue its operation, The clock CLK is continued to be supplied to the booster circuit 6 without immediately closing the gate section.

On the other hand, the second control circuit 4 uses a high-speed clock (400kHz!) which is the oscillation output of an external ceramic resonator 41.
) and a low-speed clock (32 kHz) CLK generated from the clock oscillation circuit 32 of the first control circuit 3 as operation clocks, and the code matching means 42, the calling control means 43, and the display control means 44. The code matching means 42 matches the individual number code inserted in the selective call signal supplied via the first control circuit 3 with the individual number code of the own machine stored in the memory 7. The call control means 43 is the code matching means 4.
2, when a match between the two codes is detected, the ringing signal output from the fundamental frequency generation circuit 34 of the first control means 3 is supplied to the drive circuit 81, thereby causing the speaker 82 to generate a ringing tone. .

At the same time, the message information inserted into the selective call signal is decoded to decode the message. The display control unit 44 causes the message decoded by the calling υ+m means 43 to be displayed on the display 9 made of, for example, a liquid crystal display. Note that this second control circuit 4 uses the high speed clock (400 kHz) of the two clocks for high speed operations such as code verification, and also uses the low speed clock (32 kHz).
is used for low current operation during panteri saving.

The booster circuit 6 is composed of a separately excited DC-DC converter, and converts the output voltage Vccl = 1.5 V of the battery 5 to 3V in accordance with the clock CLK generated from the clock oscillation circuit 32 of the first control circuit 3.
．． The voltage is boosted to OV, and this boosted power supply voltage Vcc2 is supplied to the second control circuit 4.

With this configuration, a power switch (not shown)
In the state in which the microprocessor is turned on, the second control circuit 4 consisting of a microprocessor receives the high-speed clock oscillated by the ceramic resonator 41 as well as the internal clock CLK generated from the clock oscillation circuit 32 of the first control circuit 3. The internal clock CLK is supplied as a low-speed clock, and the internal clock CLK is also supplied to the boost circuit 6 as a clock pulse for boosting. . Therefore, from the booster circuit 6, the clock C
The power supply voltage 'Jcc2 boosted according to LK is output and supplied to the second control circuit 4, whereby the second control circuit 4 enters the operating state. Therefore, when the selective calling signal is received and demodulated during the receiving period of the selective calling signal, the second control circuit 4 compares the individual number code inserted into the selective calling signal with the code matching means 42 and stores it in the memory 7. Check the individual number code of your own aircraft. Note that this operation is performed in synchronization with a high-speed clock (400 klb) generated from the ceramic resonator 41. and,
If the codes match as a result of this comparison, the second control circuit 4 uses the call control means to supply a ringing signal to the drive circuit 81 to generate a ring tone from the speaker 82, thereby notifying the subscriber that a call has occurred. do.

At the same time, the call control means 43 decodes the message information inserted into the selective call signal, and the display control means 44 causes the display 9 to display the decoded message. Therefore, the subscriber can recognize the occurrence of a call by the ringing tone, and can know, for example, the contact information from the displayed message by visually checking the display 9. Note that during the period when the receiver is in a low current operating state due to battery saving, the second
The control circuit 4 operates in synchronization with the clock CLK generated from the first clock oscillation circuit 32.

As described above, in this embodiment, the internal clock CLK generated from the existing clock oscillation circuit 32 is supplied as the low-speed clock of the second control circuit 4 and also as the drive clock of the booster circuit 6. By doing that,
In addition to enabling the conventional calling operation, it is possible to eliminate the need for both the low-speed clock generation circuit and the step-up clock generation circuit required for the operation of the second control circuit 4, and the circuit configuration of the receiver can be reduced accordingly. can be simplified and downsized.

Further, in this embodiment, the following effects are achieved by providing the clock control circuit 35. That is, when the subscriber turns off the power switch in the operating state, the clock control circuit 35 detects that the power switch is turned off, and at this point first outputs an operating state inquiry signal to the second control circuit 4.

In response to this, if a signal indicating that an undisplayed message remains, for example, is returned from the second control circuit 4, it is determined that it is necessary to continue operating the second control circuit 4, and the gate section Keep the gate open. Therefore, even after the battery voltage V ccl is turned off, the supply of the clock CLK to the booster circuit 6 is continued, so that the second control circuit 4 continues to maintain its operating state. Therefore, undisplayed messages are not deleted and continue to be displayed on the display 9 according to the subscriber's operations.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, the configurations of the first and second control circuits and promotion circuits, the oscillation frequency of the clock oscillation circuit, etc. may be changed without departing from the gist of the present invention. It can be implemented with various modifications.

[Effects of the Invention] As described in detail above, according to the present invention, the first system includes a synchronous circuit that performs synchronization with respect to a selective call signal, and a clock generation circuit that generates an internal clock necessary for the operation of this synchronous circuit. a second control circuit comprising a control circuit, a microprocessor for collating individual number codes and controlling a call display when the codes match, and for controlling the decoding and display of message information; and the operation of the second control circuit. A step-up circuit that generates a power supply voltage from a battery voltage, and this step-up circuit is constituted by a separately excited DC voltage converter, and the step-up circuit and the second control circuit are connected to each other to generate a clock for the first control circuit. By supplying the internal clock generated by the circuit as the operating clock, it is possible to supply a stable zero clock to the microprocessor and booster circuit without providing a new lock generation circuit. It is possible to provide a selective call receiver with a message display function that can be simplified and downsized.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing the configuration of the present invention, and FIG. 2 is a circuit block diagram of a selective call receiver according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Antenna, 2... Radio circuit part, 21... Radio circuit, 22... Demodulation circuit, 3... First control circuit, 31... Crystal resonator, 32... Clock oscillation circuit, 33... Bit synchronization circuit, 34... Fundamental frequency generation circuit, 35... Clock control circuit, 4... Second control circuit, 41... Ceramic resonator, 42... - Code checking means, 43... Calling control means, 44... Display driving means, 5... Battery, 6... Boosting circuit, 7...
Memory, 81... Drive circuit, 82... Speaker, 9
...Display, CLK...Internal clock, V cal
...Battery voltage, V OC2...Power supply voltage after boosting.

Claims (2)

[Claims] (1) Receive the selective call signal sent from the base station, compare the individual call code inserted in this signal with the individual call code of your own machine, and if the two codes match, perform a predetermined call display. In addition, in a selective call receiver that decodes and displays message information inserted in the selective call signal, a synchronization circuit that performs synchronization with the selective call signal and an internal clock necessary for the operation of this synchronization circuit are generated. a first control circuit having a clock generation circuit; and a second control circuit comprising a microprocessor that performs verification of the individual number codes and controls a call display when the codes match, and also controls the decoding and display of message information. and a booster circuit that generates the operating power supply voltage of the second control circuit from the battery voltage, the booster circuit is composed of a separately excited DC voltage converter, and the booster circuit and the second control circuit A selective call receiver, characterized in that an internal clock generated from a clock generation circuit of the first control circuit is supplied as an operating clock to the first control circuit. (2) When the supply of battery voltage to the predetermined circuit is turned off, the first control circuit controls the clock to the booster circuit if the second control circuit determines that it is necessary to continue operation. A clock control circuit that continues the supply of clocks to the booster circuit, while cutting off the supply of clocks to the booster circuit when the second control circuit determines that there is no need to continue operation. A selective call receiver according to scope (1).