JPS63190456A - Signal control circuit for identification device - Google Patents

Abstract

PURPOSE:To keep the output level of a signal amplifier within a prescribed level range by using a reset signal of a selector as a pseudo error detection signal. CONSTITUTION:The titled circuit is an automatic gain control circuit of a signal amplifier to control an input signal A of an A/D converter 2 converting an analog signal demodulating a multi-value orthogonal amplitude modulation signal into a digital code through identification into a prescribed range of level; and a is provided with selector 31 outputting selectively the bits other than the most significant bit D1 of the output data of the A/D converter 2, e.g., a 4-bit data D3 and an error signal D5 being a lower order by one bit than the least significant bit D4. Then a reset signal of the selector 31 is used as a pseudo error detection signal formed by output bits D5, D6 of the A/D converter 2 and when the input signal A is fluctuated in excess of the prescribed level range, the bit D3 is outputted from the selector, the bit D3 and the most significant bit D1 are exclusively ORed and the result is integrated, then the result is used as the control signal to control the gain of the signal amplifier 1 thereby keeping the output level of the amplifier 1 within a prescribed level.

Description

[Detailed Description of the Invention] [Summary] A signal amplifier for controlling the input signal of a D converter that identifies an analog signal demodulated from a multilevel quadrature amplitude modulation signal and converts it into a digital code within a predetermined level range. An automatic gain control circuit that selectively outputs bits other than the most significant bit 01 of the output data of the D/D converter, for example, 4-bit data D3, and an error signal D5 one bit lower than the least significant bit l-04. A selector is provided, and the selector signal is sent to the output bit D5 of the A/D converter.
, D6, when the input signal fluctuates beyond a predetermined level range,
Bit D3 is output from the selector, the exclusive OR of D3 and the most significant bit D1 is performed, and the integrated signal is used as a control signal to control the gain of the signal amplifier, so that the output level of the amplifier is within a predetermined level range. What I tried to keep.

[Industrial application field]

The present invention describes the I/O of demodulator output on the receiving side of a digital wireless communication system using multilevel quadrature amplitude modulation (QAM).
An A/D converter type identification device that identifies the levels of channel and Q channel analog signals, converts them into multi-bit digital signals, and outputs them.In particular, it is used to identify the input signal level of the A/D converter, which is a level discriminator. This invention relates to a signal control circuit that automatically controls the level within an appropriate range.

As a signal control circuit that automatically controls the input signal level of the A/D converter to an appropriate level range, it is possible to use a signal control circuit that automatically controls the input signal level of the A/D converter even if the device input level of the analog signal, which is the demodulated output of the multilevel QAM signal, fluctuates greatly due to fading in the transmission/reception section. It is desired that the level of the analog signal input to the A/D converter, which is the discriminator of the discriminator, be controlled to an appropriate value to output a correct digital signal with few code errors.

[Conventional technology]

FIG. 3 shows a conventional example of the configuration of a signal control circuit in a multilevel QAM signal identification device.

I-channel and Q-channel analog signal inputs, which are demodulated outputs of multilevel QAM signals, are input to respective amplifiers 1, amplified, output at predetermined output levels, and input to an A/D converter 2.

The A/D converter 2 identifies the input analog signal at a predetermined identification level, encodes it into a digital signal, and outputs it, but the multi-value QAM signal is 256-value QA? In the case of signals, they are identified at 16 identification levels, and are divided into 4-bit codes D1 to D1.
Output the identification data of D4.

(first bit of the most significant bit of 4-bit output data) D
Since I is a bit that is encoded by identifying the input level of the A/D converter 2 with an identification level of a DC value that is 1/2 of a predetermined total amplitude value, it is a polarity signal that represents the positive or negative polarity of the input signal. becomes.

The A/D converter 2 also outputs the lower fifth pin l-05 of the fourth bit D4 of the output data.
D5 is an error signal representing the polarity of the identification error of the output data.

In the signal control circuit of the conventional identification circuit shown in FIG. The output of the correlator 3 is the integrator 4.
are input and time averaged.

The integrator 4 applies a DC output, which is a time average of the input signal, to the amplifier 1 as a control signal C, and automatically controls the gain of the amplifier 1.

As the input signal increases, the output level of amplifier 1, that is, A
When the input signal level of the /D converter 2 increases on the positive side, the polarity signal Dl is output as "11" and the error signal D5 is also output as "11". Therefore, Dl
The output code of the correlator 3 that takes the exclusive OR of and D5 is “L
''.Then, the control signal for the DC output of the integrator 4, which integrates the output of the correlator 3, controls the gain of the amplifier 1 in the direction of decreasing, and therefore the input signal level of the A/D converter 2 decreases.

Conversely, when the input signal level on the positive side of the A/D converter 2 decreases, the polarity signal Dl is output at "H" and the error signal D5 is output at "L", so the exclusive OR of Dl and D5 is The output code of the correlator 3 that takes the value becomes "H". Then, the control signal for the DC output of the integrator 4, which integrates the output of the correlator 3, controls the gain of the amplifier 1 in the direction of increasing, and the input signal level of the A/D converter 2 increases.

Even when the input signal of the A/D converter 2 is a signal of negative polarity, similar gain control is performed on the amplifier 1, and the output level of the amplifier 1, that is, the A/D converter, changes as the input signal level increases or decreases. Automatic control is performed so that the input level of No. 2 falls within a certain level range.

[Problem that the invention seeks to solve]

The conventional signal control circuit shown in FIG. 3 operates as described above.
Although the output level of the amplifier L, that is, the input level of the ^/D converter 2, is automatically controlled to be within a certain level range in response to fluctuations in the input signal level of the amplifier L, fading in the transmission and reception sections of the wireless communication system becomes severe, and the amplifier 10 When the level fluctuation of the input signal becomes extremely large, the output level of amplifier 1, that is, the input signal level of ^/D converter 2, also changes greatly, and the level of the input signal of A/D converter 2 becomes higher than normal. A/
Error signal indicating the identification error of D converter 2) D5
outputs a sign with a polarity opposite to the normal polarity. This phenomenon also occurs when the DC offset of the amplifier 1 is abnormal.

When the polarity of the error signal bit D5 outputted by the A/D converter 2 becomes opposite to that in the normal state, the output of the correlator 3 also becomes the opposite polarity, and the polarity of the DC output of the integrator 4 also becomes opposite, so that the output of the amplifier 1 becomes the opposite polarity. The problem is that the gain is controlled in the opposite direction, does not exhibit normal control characteristics, and the control loop no longer engages.

This problem becomes particularly noticeable as the multilevel QAM modulated signal becomes more multivalued.

[Means for solving problems]

When the analog signal level input to this discriminator becomes large and the output level fluctuation of the amplifier 1 becomes large, and the input level of the A/D converter 2 of the discriminator deviates significantly from the predetermined level range, and when the DC current of the amplifier 1 becomes large. The problem that when the offset is abnormal, the gain control characteristic for the amplifier 1 of the identification device cannot converge the fluctuation of the input signal level and the control loop cannot be pulled in is solved by the present invention whose principle configuration is shown in the block diagram of FIG. be done.

In the principle block diagram of FIG. 1, 1 is an amplifier that inputs and amplifies an analog signal obtained by demodulating a multilevel orthogonal amplitude modulation signal, and 2 is an amplifier that identifies the analog signal output from the amplifier 1 and converts it into a digital signal. This is an A/D converter that converts

3 is a control signal detection means for detecting a control signal C for controlling the gain of the amplifier l from the digital output of the A/D converter 2, and includes a selector 3 and a correlator 32. Consists of. Then, the selector 31 selects a bit Di other than the most significant bit D1 of the output data D of the A/D converter 2 and a bit D that is one bit lower than the least significant bit Dn of the output data O of the A/D converter 2. This circuit inputs n+1 and selects and outputs bit Di or D n+1 using a selection signal S.

The correlator 32 is a logic gate that inputs the most significant pin 1-Di of the output data D of the A/D converter 2 and the output of the selector 31 and calculates an exclusive OR.

4 is an integrator that takes the time average of the output of the correlator 3.

5 inputs the error signal D n+1 of the A/D converter 2 and the bit D n+2, which is one bit lower than the error signal D n+1, to detect a pseudo error pulse;
This is a pseudo-error detection circuit that sends out a selection signal S that drives the selector 31 of.

[Effect]

An analog signal obtained by demodulating the multilevel orthogonal amplitude modulation signal is input to an amplifier 1 and amplified, and then input to an A/D converter 2 at a predetermined level.

The level of the analog signal input to the A/D converter 2 is identified and encoded using a plurality of predetermined identification levels, and output data D1 to Dn of n bits and an error signal of one bit lower than the n bits are output. Bit D n+1 and one bit lower bit Dn+2 are output.

The selector 31 of the control signal detection means 3 selects bits Di other than the most significant bit D1 of the output data of the A/D converter 2,
The error signal bit D n+1 which is one bit lower than the least significant bit Dn of the output data of the A/D converter 2 is input, and the bit Di or the bit D n+1 is selected and outputted by the selection signal S.

The selection signal S that drives the selector 31 is generated by a pseudo-error detection circuit that inputs the error signal bit Dn+1 output from the A/D converter 2 and its 1-bit lower bit On+2, correlates it, and detects a pseudo-error pulse. Made by 5.

The 351 selection signal S output from the pseudo error detection circuit 5 is A/
When the input analog signal of the D converter 2 is within a predetermined level range, it is output with a sign "O", but when it fluctuates outside the predetermined level range, it is output with a sign "H".

When the selection signal S is "H", the selector 31 selects and outputs the bit Di, and when the selection signal S is "L", the selector 31 selects and outputs the focus D n+1.

The output D of the selector 31 is selectively outputted by the selection signal S.
i or On+1 is input to the correlator 32, and at the same time the A/D
Most significant bit Dl of output data input from converter 2
An exclusive OR is taken.

The output of the correlator 32 is input to the integrator 4, time-averaged, and outputted as a control signal C in the form of a DC signal.

A control signal C for the DC output of the integrator 4 is applied to the amplifier 1 to control its amplification gain so that the output level falls within a certain level range.

By the way, the control characteristic based on the exclusive OR of the most significant bit DI of the output data and the bits Di other than D1 is the most significant bit D1 of the output data and the error signal bit D n+
The pull-in range for the input level is wider than the control characteristic based on the exclusive OR of 1.

Therefore, even when the analog signal input to the A/D converter 2 fluctuates beyond a predetermined level range, the selection signal S output from the pseudo error detection circuit 5 becomes "11" and drives the selector 31. The correlator 32 calculates the exclusive OR of the most significant bit D1 of the output data and the bit Di and outputs the result. At this time, the control signal output from the integrator 4 The pull-in range of the control loop by C is widened, the control is reliably pulled in, and the output level of the amplifier 1, that is, the input level of the A/D converter, is maintained within a predetermined level range, and the problem is solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the signal control circuit of the identification device according to the embodiment of the present invention.
1 is an example of a value QAM signal. The analog signals obtained by demodulating the multi-level QA1 signal are divided into channel (1) and Q channel, but only one is shown in the figure.

The amplifier 1 is an amplifier that inputs and amplifies an analog signal obtained by demodulating a 256-value QAM signal, and the A/D converter 2
This is an A/D converter that identifies the analog signal output from the amplifier 1 and converts it into 4-bit output data D1 to D4.

The control signal detection means 3 is a circuit for detecting a control signal C for controlling the gain of the amplifier 1 from the output of the A/D converter 2, and is an exclusive OR circuit of the selector SEL of the selector 31 and the correlator 32. Consists of EX-OR.

The selector SEL of the selector 31 selects bits D other than the most significant bit D1 of the output data Di-04 of the A/D converter 2.
3, and the least significant bit D of the output data of the A/D converter 2
This circuit inputs the via (D5) which is one bit lower than 4 and selects and outputs pins 1-D3 or D5 according to the reset/cent signal of the selection signal S.

The exclusive OR circuit EX-OR of the correlator 32 is a logic circuit that inputs the most significant bit D1 of the output data of the A/D converter 2 and the output of the selector SEL of the selector 31 and performs an exclusive OR correlation. It is a gate.

The integrator 4 is an integrator that integrates the output of the gate EX-OR of the correlator 3 and takes the time average.

The pseudo error detection port H5 inputs the error signal P1-05 of the output of the A/D converter 2 and the PIT D6 which is one bit lower than the bit D5, performs an exclusive OR, and detects a pseudo error pulse. Exclusive OR circuit EX-OR51 and the EX-O
An integrator 52 that integrates the output of R51 and a comparator 53 that compares the output of the integrator 52 with a reference voltage and outputs a comparison signal.
The comparison signal is "L" when the input analog signal A of the A/D converter 2 is within a predetermined level range, and is "H" when it is out of the predetermined level range. be done.

This comparison signal is sent to the selector 3 of the control signal detection means 3.
This becomes a set/reset selection signal S of 1.

The comparison signal output from the pseudo-error error detection circuit 5 is “YES”.
When it is a sign, the selector 31 is set and the bit D5 is selectively output from the selector 31, and the pseudo lHA detection circuit 5
When the output signal is "H" code, the selector 31 is reset and the selector 31 outputs bit D3.

The selected output D3 or D5 of the selector 31 is input to the logic game of the correlator 32) and the correlation of the exclusive OR with the highest pin point D1 of the output data inputted to the EX-OR and simultaneously inputted from the A/D converter 2. Be taken.

The output of the correlator 32 is integrated by an integrator 4 and becomes a DC output control signal C, which controls the gain of the amplifier 1 and maintains its output level within a certain level range.

By the way, the most significant bit D1 of the output data of the A/D converter 2
The control characteristic based on the exclusive OR of the bit D3 other than the bit D1 has a wider pull-in range for the input level than the control characteristic based on the exclusive OR of the most significant bit DI and the error signal bit D5.

Therefore, even when the analog input signal of the A/D converter 2 fluctuates beyond a predetermined level range, the pseudo error detection circuit 5
The comparison signal outputted by becomes "H", resets the selector 31, causes the selector 31 to output a beep (D3), and the correlator 32 compares the highest focus DI of the output data of the A/D converter 2 with the selector 31. Since it is output after taking the exclusive OR with the output bit D3, at this time, the control by the control signal C output from the integrator 4 has a wide pull-in range, and is reliably pulled into the control loop. The output level of the A/D converter, that is, the input level A of the A/D converter is maintained within a predetermined level range, and the problem disappears.

This control operation is similar even when the DC offset of the amplifier 1 is abnormal, and it is possible to maintain the input level 8 of the A/D converter within a predetermined level range.

〔Effect of the invention〕

As explained above, according to the present invention, the level of the input signal of the discriminator varies due to fading, and the input level of the A/D converter of the discriminator greatly deviates from the normal level range. Even when the DC offset of the preamplifier placed in front of it becomes abnormal, the input signal is reliably drawn into the control loop, controlling the gain of the preamplifier and keeping its output level within a certain level range. Therefore, the effect of improving the stability of the identification device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram showing the configuration of the signal control circuit of the identification device of the present invention, FIG. 2 is a block diagram showing the configuration of the signal control circuit of the identification device of the embodiment of the present invention, and FIG. 3 is the conventional one. FIG. 3 is a block diagram of a signal control circuit of the identification device. 1 and 2, 1 is an amplifier, 2 is an A/D converter, 3 is a control signal detection means, and 31 is a selector SEL. 32 is a correlator, exclusive OR circuit EX-OR14 is an integrator, 5 is a pseudo error detection circuit, and 51 is exclusive OR circuit EX-OR. 52 is an integrator, and 53 is a comparator.

Claims (1)

[Scope of Claims] An input signal level control circuit of an identification device inputs an analog signal obtained by demodulating a multilevel orthogonal amplitude modulation signal, controls the level within a predetermined range, and encodes the signal for identification, and amplifies the analog input signal. An amplifier (1), and an A/A that identifies the analog signal (A) output from the amplifier (1) and converts it into a plurality of n-bit digital signals (D).
D converter (2) and digital signal (D) output from the A/D converter (2)
The bits (Di) other than the most significant bit (D1) of the digital signal (D) and the error signal bit (Dn+1) which is one bit lower than the least significant bit (Dn) of the digital signal (D) are input to generate the selection signal (
S) the bit (Di) or bit (Dn+1)
A selector (31) that selects and outputs the output of the selector (31) and the most significant bit (D1) of the digital signal (D)
A control signal detecting means (3) comprising a correlator (32) that takes the exclusive OR of the control signal detecting means (3), and a control signal (3) for controlling the gain of the amplifier (1) that takes the time average of the output of the control signal detecting means (3). C) and an error signal bit (D) output from the A/D converter (2).
n+1) and the bit (Dn+2) which is one bit lower than the bit (Dn+1), the correlation is taken, a pseudo error pulse is detected, and the selector (3) of the control signal detection means (3)
It consists of a pseudo error detection circuit (5) that outputs a selection signal (S) that drives the A/D converter (2) by the selection signal (S) output from the pseudo error detection circuit (5). When the input analog signal (A) is within a predetermined level range, the selector (31) selects and outputs the bit (Dn+1), and when the analog signal (A) is outside the predetermined level range, The selector (31) selectively outputs the bit (Di), and the output of the integrator (4) controls the gain of the amplifier (1) to set the output level of the amplifier (1) to a predetermined level. A signal control circuit for an identification device characterized by maintaining the signal within a level range.