JPS63190358A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS63190358A JPS63190358A JP2174287A JP2174287A JPS63190358A JP S63190358 A JPS63190358 A JP S63190358A JP 2174287 A JP2174287 A JP 2174287A JP 2174287 A JP2174287 A JP 2174287A JP S63190358 A JPS63190358 A JP S63190358A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- film
- wiring layer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 54
- 239000000758 substrate Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 9
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体素子の製造方法に係り、特に多層配線
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor element, and particularly to a method for forming multilayer wiring.
（従来の技術）
従来技術として、タングステン（Ｗ）選択ＣＶＤ法を用
いた多層配線の形成方法を第２図を用いて説明する。ま
ず、Ｓｌ基板１１にトランジスタ等を形成し、ＣＶＤ
（化学気相成長法）等の方法で中間絶縁膜１２（例えば
５ｉｎ２． ＰＳＧ）を形成する。次いで、その中間絶
縁膜１２にコンタクトホール１３を開孔後、ＡＩ系合金
をスパッタ等の方法でデポジションしてホトリソ・エツ
チングを施し第１配線層１４とする。その後、層間絶縁
膜１５をＣＶＤ。(Prior Art) As a conventional technology, a method for forming multilayer wiring using tungsten (W) selective CVD method will be described with reference to FIG. First, transistors and the like are formed on the Sl substrate 11, and then CVD
The intermediate insulating film 12 (for example, 5 in 2. PSG) is formed by a method such as chemical vapor deposition (chemical vapor deposition). Next, after a contact hole 13 is opened in the intermediate insulating film 12, an AI alloy is deposited by sputtering or the like, and photolithography and etching are performed to form a first wiring layer 14. After that, the interlayer insulating film 15 is formed by CVD.
スパッタ等の方法でデポジションし、それにスルーホー
ル１６を開孔する。次に、減圧雰囲気中で基板を３００
〜５００℃に加熱しながら八と六弗化タングステン（Ｗ
Ｆ ６）を１： １０〜１：２００の割合で流す。この
時、圧力を約ＩＴｏｒｒ程度にしておくと、スルーホー
ル１６内の第１配線層（１）１４上にのみ選択的にＷ層
１７が成長する。このＷ層１７を５０００人程度成長さ
せ、アスペクト比（スルーホールの深さ／スルーホール
径の比）を小さくした後、ＡＩ系合金をスパッタ等でデ
ポジションし第２配線層１８とする。以上の方法により
、段切れのない多層配線を形成することができる。以上
、第１の方法とする。It is deposited by a method such as sputtering, and a through hole 16 is formed therein. Next, the substrate was heated for 300 minutes in a reduced pressure atmosphere.
Tungsten octa- and hexafluoride (W) while heating to ~500℃
F6) at a ratio of 1:10 to 1:200. At this time, if the pressure is kept at about ITorr, the W layer 17 selectively grows only on the first wiring layer (1) 14 inside the through hole 16. After growing this W layer 17 by about 5,000 layers and reducing the aspect ratio (ratio of through-hole depth/through-hole diameter), an AI-based alloy is deposited by sputtering or the like to form the second wiring layer 18. By the above method, it is possible to form a multilayer interconnection with no breaks. The above is the first method.
次に、従来技術のもう一つの方法としてＡＪＣＶＤによ
る多層配線の形成方法を第３図に示す。この方法では、
第１の方法と全く同様の工程で層間絶縁膜１５までを形
成し、スルーホール１６を開孔する。次いで、減圧雰囲
気中で基板を２５０〜３００℃に加熱する。次に、トリ
イソブチルアルミニウム（ＴＩＢＡ）の液体をバブラー
管内で加熱し、馬ガスによりバブラーする乙とによって
取り出したＴＩＢＡと川の混合ガスを基板表面に導く。Next, FIG. 3 shows a method of forming multilayer wiring by AJCVD as another conventional method. in this way,
In exactly the same steps as in the first method, layers up to the interlayer insulating film 15 are formed, and through holes 16 are opened. Next, the substrate is heated to 250 to 300°C in a reduced pressure atmosphere. Next, a liquid of triisobutylaluminum (TIBA) is heated in a bubbler tube, and the mixed gas of TIBA and river extracted by the bubbler tube is introduced to the substrate surface.
この結果、ＴＩＢＡは基板表面（層間絶縁膜１５表面）
で熱分解され、スルーホール１６を埋めて層間絶縁膜１
５の表面に１’をデポジションし、第２配線層１９とな
る。As a result, TIBA is formed on the substrate surface (interlayer insulating film 15 surface).
is thermally decomposed, filling the through hole 16 and forming the interlayer insulating film 1.
1' is deposited on the surface of 5 to form a second wiring layer 19.
乙のＡＩ ＣＶＤを用いる方法では、基板表面での反応
のため、スパッタ法に比べＡＪのステップカバレージが
良く、かつエレクトロマイグレーションの影響のない多
層配線を形成することができる。In the method using AI CVD, since the reaction occurs on the substrate surface, AJ step coverage is better than in the sputtering method, and multilayer wiring can be formed without being affected by electromigration.
（発明が解決しようとする問題点）
しかしながら近年、デバイスの集積化・高密度化に伴い
配線、層間膜の平坦化が強く求められて来ている。その
結果、層間絶縁膜の平坦化法、（例えばバイアススパッ
タ法）により第４図に示すように、場所によっては２μ
ｍ程度の深いスルーホール１６が生じることとなった。(Problems to be Solved by the Invention) However, in recent years, with the increasing integration and density of devices, there has been a strong demand for flattening of wiring and interlayer films. As a result, as shown in FIG.
A through hole 16 having a depth of approximately 1.0 m was formed.
しかしながら、Ｗ選択ＣＶＤ法を用いると、現状では５
０００〜７０００人程度成長すると成長激に選択性を失
い、層間絶縁膜１５上にも堆積が始まる。よって、選択
性を維持できる５０００人程度成長を選択成長させたと
しても、スルーホール１６内は依然１μｍ以上の深さが
あり、第２図に示す第２配線層１８の段切れが生じるこ
とになる。However, if the W selection CVD method is used, currently 5
When the number of particles grows to about 000 to 7000, the selectivity is lost due to rapid growth, and deposition also begins on the interlayer insulating film 15. Therefore, even if selective growth is performed to maintain selectivity of about 5,000 layers, the inside of the through hole 16 will still have a depth of 1 μm or more, and a break in the second wiring layer 18 as shown in FIG. 2 will occur. Become.
次に、ＡｔｌＣＶＤ法を用いた場合、深いスルーホール
１６でも第２配線層１９のカバレージに関しては全く問
題は生じない。しかしながら、現状のＡｌＣＶＤ技術で
は金属を下地膜とした場合は、品質の良いＡｌ膜（第２
配線層１９）が得られてし）るが、下地膜が絶縁膜の場
合、結晶成長する過程で結晶の中心となる核の形成がし
に＜＜、その結果表面の凹凸が甚しく、膜質も密度が粗
なＡｌ膜しか得られない。また、得られるＡｌ膜は、純
Ａｊ金属であるため、第１配線層１４から、またその下
の拡散層からＳｉが拡散混入するため、デバイスに悪影
響を与えるという問題がある。Next, when the AtlCVD method is used, no problem arises in terms of coverage of the second wiring layer 19 even with the deep through holes 16. However, with the current AlCVD technology, when metal is used as the base film, it is difficult to obtain a good quality Al film (second
A wiring layer 19) is obtained, but when the underlying film is an insulating film, the formation of a nucleus that becomes the center of the crystal during the crystal growth process is difficult, resulting in severe surface unevenness and poor film quality. However, only an Al film with a coarse density can be obtained. Furthermore, since the obtained Al film is a pure Aj metal, Si is diffused and mixed in from the first wiring layer 14 and from the diffusion layer below, which has a problem of adversely affecting the device.
この発明は、以上述べたＷ選択ＣＶＤ法、ＡＪＣＶＤ法
を応用発展させることによね、２μｍ前後の深いスルー
ホールにおいても段切れを防止でき、かっＳｉの拡散と
いった問題点を解決でき、しかも高品質のＡｌ膜による
多層配線を形成することのできる半導体素子の製造方法
を提供することを目的とする。By applying and developing the above-mentioned W selection CVD method and AJCVD method, this invention can prevent breakage even in deep through holes of around 2 μm, solve problems such as Si diffusion, and achieve high quality. An object of the present invention is to provide a method for manufacturing a semiconductor element that can form multilayer wiring using an Al film.
（問題点を解決するための手段）
この発明では、下地上に第１配線層を形成し、その上に
絶縁膜を形成し、この絶縁膜に前記第１配線層に貫通す
るスルーホールを開けた後、そのスルーホールの第１配
線層上にＷを選択的に成長させ、引き続きＷの非選択成
長を行うことにより、−４＝
前記第１配線層上とともに、スルーホールの内壁を含む
前記絶縁膜の表面にＷを成長させ、その後、前記Ｗを下
地としてＡｔ’ ＣＶＤ法により第２配線層としてＡｌ
膜を、前記スルーホールを埋めて前記絶縁膜上に形成す
る。(Means for Solving the Problems) In the present invention, a first wiring layer is formed on a base, an insulating film is formed on the first wiring layer, and a through hole is formed in this insulating film to penetrate the first wiring layer. After that, by selectively growing W on the first wiring layer of the through hole and then non-selectively growing W, -4= the above-mentioned area including the inner wall of the through hole as well as on the first wiring layer. W is grown on the surface of the insulating film, and then Al is grown as a second wiring layer by At' CVD using the W as a base layer.
A film is formed on the insulating film filling the through hole.
（作 用）
上記のような方法においては、スルーホールが２μｍＷ
後と深いスルーホールであっても、ＡＪＣＶＤ法により
、良好なステップカバレージを有して第２配線層として
のＡｌ膜が形成される。また、そのＡｌ膜は、下地のＷ
を結晶の核として結晶が成長するため、下地が絶縁膜の
場合と比べはるかに凹凸の少ない密な良質のＡｌ膜とな
る。また、その第２配線層としてのＡｌ膜と第１配線層
間には下地Ｗが介在され、この下地Ｗは、第１配線層か
ら第２配線層にＳｉが拡散混入されることを防止するバ
リアメタルとして働く。(Function) In the above method, the through hole is 2 μmW.
Even in the case of deep through-holes, an Al film as a second wiring layer is formed with good step coverage by the AJCVD method. In addition, the Al film is
Since the crystals grow using the crystals as crystal nuclei, a dense, high-quality Al film with far fewer irregularities is formed than when the underlying layer is an insulating film. Further, a base W is interposed between the Al film as the second wiring layer and the first wiring layer, and this base W is a barrier that prevents Si from being diffused and mixed from the first wiring layer to the second wiring layer. Works as a metal.
（実 施 例） 以下乙の発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the invention of B will be described below with reference to FIG.
まず、第１図（ａｌに示すように、Ｓｉ基板２１上にト
ランジスタを形成した後、中間絶縁膜２２、第１配線層
２３、層間絶縁膜２４を順次形成し、層間絶縁膜２４に
は第１配線層２３に貫通するスルーホール２５を開孔す
る。First, as shown in FIG. A through hole 25 penetrating through the first wiring layer 23 is opened.
次に、減圧雰囲気中で基板を３００〜５００℃に加熱し
ながらＨ２とＷＦ６を１： １０〜１：２００の割合で
チャンバー内に流す。この時、圧力を約ＩＴ’ｏｒｒ程
度とする。すると、第１図（６）に示すように、スルー
ホール２５内のＡＩ系合金からなる第１配線層２３上に
のみＷ層２６が成長する。そして、このＷ層２６が約５
０００成長度まで選択的に成長したところで基板にＵＶ
光を照射する。Next, H2 and WF6 are flowed into the chamber at a ratio of 1:10 to 1:200 while heating the substrate to 300 to 500[deg.] C. in a reduced pressure atmosphere. At this time, the pressure is set to approximately IT'orr. Then, as shown in FIG. 1(6), the W layer 26 grows only on the first wiring layer 23 made of an AI alloy in the through hole 25. This W layer 26 is about 5
After selectively growing to a growth degree of 0.000, the substrate is exposed to UV light.
Irradiate light.
すると、基板表面が活性化され、層間絶縁膜２４上でも
ＷＦ６の吸着、分解が起こるようになる。この時の反応
を次式に示す。Then, the surface of the substrate is activated, and adsorption and decomposition of WF6 also occur on the interlayer insulating film 24. The reaction at this time is shown in the following formula.
ＵＶ基板照射
エネルギｈν
ＷＦ６＋３Ｈ２−Ｗ＋６ＨＦ↑
したがって、上記ＵＶ光照射後は、スルーホール２５内
の第１配線層２３上とともに、前記第１図（ｂｌに示す
ように、スルーホール２５の内壁を含む層間絶縁膜２４
の表面にＷ層２７が形成されるようになる。そして、層
間絶縁膜２４上にＷ層２７が２０００人程度堆積された
ところで、Ｗのデポジションを終了する。UV substrate irradiation energy hν WF6+3H2-W+6HF↑ Therefore, after the above-mentioned UV light irradiation, not only the first wiring layer 23 in the through hole 25 but also the interlayer including the inner wall of the through hole 25 as shown in FIG. Insulating film 24
A W layer 27 is formed on the surface of the wafer. Then, when about 2000 W layers 27 are deposited on the interlayer insulating film 24, the W deposition is terminated.
そして、上記のようにしてＷ層２６，２７を形成したな
らば、次に、そのＷ層２６．２７を下地としてＡｌＣＶ
Ｄ法により第２配線層としてのＡＩ膜２８を第１図（Ｃ
）に示すようにスルーホール２５を埋めて層間絶縁膜２
４上に形成する。その場合の具体的方法としては、まず
、Ｗのデポジションに用いたＷＦ６をチャンバーから完
全に排気した後、減圧中で基板を２５０〜３００℃に加
熱する。次に、ＴＩＢＡの液体をバブラー管に封入し、
約５０℃に加熱しながらへガスによりバブラーする。乙
の結果、ＴＩＢＡの気化ガスを含んｔ！馬ガスを得る。After forming the W layers 26 and 27 as described above, next, the W layers 26 and 27 are used as a base to form an AlCV film.
The AI film 28 as the second wiring layer is formed by the D method as shown in FIG.
), the through hole 25 is filled and the interlayer insulating film 2 is
4. Form on top. As a specific method in that case, first, after completely exhausting the WF6 used for W deposition from the chamber, the substrate is heated to 250 to 300° C. under reduced pressure. Next, TIBA liquid is sealed in a bubbler tube,
Bubble with gas while heating to about 50°C. As a result, t! contains TIBA vaporized gas! Get horse gas.
この混合ガスを加熱した基板表面に導くと、ＴＩＢＡの
熱分解温度は２２０℃以上であるから、基板表面（スル
ーホール２５および層間絶縁膜２４上のＷ層２６．２７
表面）に吸着したＴＩＢＡは、Ａｌ−７＝
とその他の炭素化合物気体に分解し、スルーホール２５
と層間絶縁膜２４上に１’を堆積する。そして、このよ
うにしてＡＩ膜２８を約１μｍ堆積させた後、ホトリソ
・エツチングを施し、第２配線層を形成する。When this mixed gas is introduced to the heated substrate surface, since the thermal decomposition temperature of TIBA is 220° C. or higher,
TIBA adsorbed on the surface) decomposes into Al-7= and other carbon compound gases, and the through hole 25
and 1' are deposited on the interlayer insulating film 24. After the AI film 28 is deposited to a thickness of approximately 1 μm in this manner, photolithography and etching are performed to form a second wiring layer.
なお、発明者の実験では、ＣＶＤ Ｗ層２６．２７を下
地として得られるＡＩ膜２８は成長段階で下地のＷを結
晶の核として結晶粒が成長を始めるため、下地が絶縁膜
である場合に比べて、ＡＪの結晶粒は小さく、結果とし
て表面が滑らかで密度の高い高品質のＡ４膜が得られて
いる。また、ＣｖＤによって得られたＡＩ膜２８中への
第１配線層２３からのＳｉの拡散は、下地Ｗ層２６．２
７がバリアメタルとして働くため、全く生じなかった。In addition, in the inventor's experiments, in the AI film 28 obtained using the CVD W layer 26, 27 as a base, crystal grains begin to grow using the W in the base as crystal nuclei during the growth stage, so when the base is an insulating film, In comparison, the crystal grains of AJ are small, resulting in a high-quality A4 film with a smooth surface and high density. Further, the diffusion of Si from the first wiring layer 23 into the AI film 28 obtained by CvD is caused by the diffusion of Si from the base W layer 26.2.
Since No. 7 acts as a barrier metal, it did not occur at all.
また、ＷＣＶＤの非選択成長させる方法として上記一実
施例では、基板にＵＶ光を照射する方法を採用したが、
他にも、川をプラズマ分解する方法、気相中にエキシマ
・レーザを照射する方法などがある。これらを用いても
よい。Furthermore, in the above embodiment, a method of irradiating the substrate with UV light was adopted as a method for non-selective growth by WCVD.
Other methods include plasma decomposition of rivers and irradiation of excimer lasers into the gas phase. You may use these.
（発明の効果）
以上詳細に説明したように、乙の発明の製造方法によれ
ば、スルーホールが２μｍ前後と深いスルーホールであ
っても、ＡｌＣＶＤ法により良好なステップカバレージ
を持って第２配線層としてのＡＪ膜を形成することがで
き、第２配線層の段切れを防止できる。また、スルーホ
ールに選択的にＷを形成した後に、連続的にＷの非選択
的成長へと移行するので、スルーホールの選択的Ｗ層と
非選択的Ｗ層との間に構造・電気特性において均一なＷ
膜が得られる。また、乙のＷの成長と同一反応チャンバ
ー中でＡｊ ＣＶＤ法による、ＡＩ膜のデボジシランを
行えるので、ＷとＡＩの界面には各々の酸化膜層や不純
物が全く混入しないという効果と、下地のＷを核として
結晶が成長するため、下地が絶縁膜の場合と比べはるか
に凹凸の少ない密な良質のＡＩ膜を第２配線層として得
られるという効果がある。さらに、スルーホールの下地
Ｗ層は第１配線層側からの第２配線層に対するＳｉの拡
散混入に対するバリアメタルとして働くので、このＳｉ
の拡散混入を無くすことができる。また、ＡＩとＷは一
体としてＡ１／Ｗｉｉｌ！線と考えることができ、Ａｌ
／Ｗ配線は衆知の如く、ヒロックやエレクトロマイグレ
ーシリンに強いという利点もあり、低抵抗、高信頼性の
平坦なメタル配線を形成できる。さらにスルーホール部
でのＷとＡＩ膜の接触面積は非選択Ｗなしに比べて大き
くなるので、接触抵抗も小さくできる。(Effects of the Invention) As explained in detail above, according to the manufacturing method of the invention of Part B, even if the through hole is as deep as about 2 μm, the second wiring can be formed with good step coverage using the AlCVD method. An AJ film can be formed as a layer, and breakage of the second wiring layer can be prevented. In addition, after W is selectively formed in the through-hole, the transition to non-selective growth of W occurs continuously, so that the structural and electrical characteristics between the selective W layer and the non-selective W layer of the through-hole are uniform W at
A membrane is obtained. In addition, since the AI film can be devodisilated by the Aj CVD method in the same reaction chamber as the W growth described above, there is an effect that no oxide film layer or impurities are mixed in at the interface between W and AI, and that the underlying layer is Since crystals grow with W as the nucleus, it is possible to obtain a dense, high-quality AI film as the second wiring layer with far fewer irregularities than when the underlying layer is an insulating film. Furthermore, since the underlying W layer of the through hole acts as a barrier metal against diffusion and mixing of Si from the first wiring layer side into the second wiring layer, this Si
Diffusion and contamination can be eliminated. Also, AI and W are integrated into A1/Wil! It can be thought of as a line, and Al
As is well known, the /W wiring has the advantage of being resistant to hillocks and electromigration, and can form flat metal wiring with low resistance and high reliability. Furthermore, since the contact area between the W and the AI film at the through-hole portion is larger than that without the non-selected W, the contact resistance can also be reduced.
第１図はこの発明の半導体素子の製造方法の一実施例を
示す工程断面図、第２図は従来の多層配線の形成方法の
第１の例を示す断面図、第３図は従来の多層配線の形成
方法の第２の例を示す断面図、第４図は眉間絶縁膜の平
坦化法により深いスルーホールが生じた場合の断面図で
ある。
２１・・・Ｓｉ基板、２２・・・中間絶縁膜、２３・・
第１配線層、２４・・・層間絶縁膜、２５・・・スルー
ホール、２６，２７・・・Ｗ層、２８・・・ＡＩ膜。FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a semiconductor element of the present invention, FIG. 2 is a cross-sectional view showing a first example of a conventional method for forming multilayer wiring, and FIG. FIG. 4 is a cross-sectional view showing a second example of the wiring formation method, and is a cross-sectional view when a deep through hole is created by the method of flattening the glabella insulating film. 21... Si substrate, 22... Intermediate insulating film, 23...
1st wiring layer, 24... interlayer insulating film, 25... through hole, 26, 27... W layer, 28... AI film.
Claims (1)
ールを形成する工程と、 （ｄ）そのスルーホールの第１配線層上にＷを選択的に
成長させる工程と、 （ｅ）引き続きＷの非選択成長を行うことにより、前記
第１配線層上とともに、スルーホールの内壁を含む前記
絶縁膜の表面にＷを成長させる工程と、 （ｆ）そのＷを下地としてＡｌＣＶＤ法により第２配線
層としてＡｌ膜を、前記スルーホールを埋めて前記絶縁
膜上に形成する工程とを具備してなる半導体素子の製造
方法。[Claims] (a) a step of forming a first wiring layer on a base; (b) a step of forming an insulating film thereon; and (c) a step of penetrating the first wiring layer through the insulating film. (d) selectively growing W on the first wiring layer of the through hole; (e) continuing non-selective growth of W to (f) growing W on the surface of the insulating film, including the inner walls of the through holes as well as on the layers; 1. A method for manufacturing a semiconductor device, comprising a step of forming it on an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2174287A JPS63190358A (en) | 1987-02-03 | 1987-02-03 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2174287A JPS63190358A (en) | 1987-02-03 | 1987-02-03 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190358A true JPS63190358A (en) | 1988-08-05 |
Family
ID=12063526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2174287A Pending JPS63190358A (en) | 1987-02-03 | 1987-02-03 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190358A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987099A (en) * | 1989-12-29 | 1991-01-22 | North American Philips Corp. | Method for selectively filling contacts or vias or various depths with CVD tungsten |
| JPH06224190A (en) * | 1992-10-30 | 1994-08-12 | Hyundai Electron Ind Co Ltd | Manufacture of tungsten plug |
-
1987
- 1987-02-03 JP JP2174287A patent/JPS63190358A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987099A (en) * | 1989-12-29 | 1991-01-22 | North American Philips Corp. | Method for selectively filling contacts or vias or various depths with CVD tungsten |
| JPH06224190A (en) * | 1992-10-30 | 1994-08-12 | Hyundai Electron Ind Co Ltd | Manufacture of tungsten plug |
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