JPS63187161A - Detection circuit for detecting duty cycle of signal - Google Patents

Abstract

PURPOSE:To deal with the variation of a time constant, by forming a retriggerable monomultivibrator wherein the time constant is set corresponding to a limit value from a trigger circuit, a lamp voltage generating circuit and a voltage comparator of which the reference voltage is subjected to feedback control. CONSTITUTION:The input signal having an average cycle tau0 through a limiter LIMIT is supplied to a retriggerable monomultivibrator RTMM1a having a time constant slightly shorter than the one-cycle length of a lower limit and a positive polarity detection pulse is outputted during a period of reference voltage Vs or less trigger circuit TRC1, a lamp voltage generating circuit REG1 and a voltage comparator COMP1. Since this voltage Vs is the one wherein the output of the comparator COMP1 is subjected to feedback control through an integration circuit INTC and a variable amplifier A to which set voltage is supplied, a detection pulse having the cycle tau0 and a predetermined ratio is outputted from the comparator COMP1 when input is a duty cycle of a lower limit length or more even when the time constant is changed by the characteristic irregularity of a constitutional element or temp. The detection of a duty cycle of an upper limit length or less is similarly performed.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is intended to solve abnormal conditions in signals caused by discontinuities in the phase of signals caused by signal dropouts or noise contamination that occur in communications and recording/reproduction signals. The present invention relates to a circuit for detecting the duty cycle of a signal to be detected.

(Conventional Technique vR) Signal duty cycle used to detect signal abnormalities caused by discontinuities in signal phase due to signal dropouts and noise contamination that occur in communications and recording/reproduction signals. As detection circuits, for example, detection circuits for missing signals, and various other configurations have been known.

FIG. 3 shows a duty cycle detection circuit previously proposed by the applicant company 1. In the duty cycle detection circuit shown in FIG. 3, 1 indicates a signal whose duty cycle is to be detected. This is an input terminal for Si (eg, frequency modulated wave signal).

Further, LMI, T is a limiter, RTMMI is a signal in a normal state of the signal Si whose duty cycle is detected, and which is triggered at the time position of the leading edge of the output pulse PQ from the limiter LMIT mentioned above. The shortest time length τO in the range of change in the time length of one cycle of
The first retriggerable monostable multivibrator is set to a time constant (time length TI) slightly shorter than
RTMM2 is triggered at the time position of the leading edge of the output pulse P1 of the first retriggerable monostable multivibrator RTMMI, and also detects one of the signals Si in the normal state whose duty cycle is to be detected It is a second retriggerable monostable multivibrator whose time constant (time length T2) is set to be slightly longer than the longest time length τ0 in the range of change of the cycle time length τO, and furthermore, PS is the second retriggerable monostable multivibrator. Output pulse P of retriggerable monostable multivibrator RTMM2
A pulse expansion circuit (for example, a pulse expansion circuit) that generates an output pulse Pa (discrimination signal) with a predetermined pulse width To from the time position of the trailing edge of 2.

It is a monostable multivibrator).

Detection of the duty cycle as shown in (,) of FIG. 4 via input terminal 1 to the limiter LMIT in the previously proposed signal duty cycle detection circuit shown in FIG. When the target signal Si is supplied, the limiter LMIT to which the input signal Si is supplied produces the signal Si shown in FIG. 4(b) corresponding to the signal Si supplied thereto. A pulse Pρ is output.

The signal Si whose duty cycle is to be detected and which is supplied to the input terminal 1 of the signal duty cycle detection circuit illustrated in FIG. The state is normal during the period of
The signal waveform in the period 2→t4 (τ1) is abnormal, and a phase discontinuity occurs at time t6, and the signal waveform in the period t5→t6 (τ2) is abnormal. It is a thing when it is a thing.

Now, when a pulse P2 as shown in FIG. 4(b) outputted from the limiter LMIT described above is supplied as a trigger pulse to the first retriggerable monostable multivibrator RTMMI.

The first retriggerable monostable multivibrator RTMMI is such that it is triggered at each time position of the leading edge of the output pulse PQ of the limiter LMIT and generates an output pulse with a predetermined pulse width T1 every time it is triggered. perform an action.

As described above, the first retriggerable monostable multi-bibreak RTMMI receives the signal Si supplied to the input terminal 1 and whose duty cycle is to be detected.
When τO is the time length of one cycle in a normal state, the time constant of the first retriggerable monostable multivibrator is set to T1, which has a relationship of τO>T1 with respect to T0. The output pulse P1 output from the RTMMI is generated when the period of the signal Si supplied to the input terminal 1 is set to the first retriggerable monostable multivibrator RTMMI, as shown in FIG. 4(C). In the case of a state longer than the time constant T1,
As shown in the period from time t1 to time t3, the period from time t4 to time t5, and the period after time t7 in (Q) of FIG.
The time length of the high level from the time position of the leading edge of the output pulse PQ of T generates the pulse of T1, and the period of the signal Si supplied to the input terminal 1 is as shown in FIG.
In a period shorter than the time constant T1 set in the first retriggerable monostable multivibrator RTMMI, such as the period from time t5 to time t6 in c), the output pulse from the limiter LMIT at time t5 By triggering the first retriggerable monostable multivibrator RTMMI at the time position of the leading edge of PQ, the output pulse Pi is kept at a high level for a time length from time t5 to T1.
Retriggerable monostable multivibrator RTMM1
Because the first retriggerable monostable multivibrator RTMMI is retriggered at the time position of the leading edge of the output pulse PQ from the limiter LMIT at time t6 during the period when the output pulse P1 from the limiter LMIT is in a high level state. , the first retriggerable monostable multivibrator R
The output pulse P1 from TMMI has a time length T from time t6.
The first retriggerable monostable multivibrator RTM continues to be at a high level for 1, changes to a low level at time tc, and then changes to a low level at time t7 at the time position of the leading edge of the output pulse PQ from the limiter LMIT.
By triggering ML, the output pulse P1 from the first retriggerable monostable multivibrator RTMMl is set to a high level state from time t7.

The second retrigable monostable multivibrator RTMM2, to which the output pulse P1 from the first retriggerable monostable multivibrator RTMMI described above is supplied as a 1 trigger, has a duty cycle that is supplied to the input terminal 1. When the time length of one cycle of the signal Si to be detected is in a normal state is T0, the time constant of the time length T2 is set in the relationship of τo(T2) with respect to T0, As shown in FIG. 4(d), the output pulse P2 output from the second retriggerable monostable multivibrator RTMM2 is the output pulse P1 output from the first retriggerable monostable multivibrator RTMMI. In other words, when the time interval between adjacent time positions of the leading edges of is longer than the time length T2, that is.

A state in which the first retriggerable monostable multivibrator RTMMI is not triggered for a time period longer than the time constant T2 set in the second retriggerable monostable multivibrator RTMM2 due to a signal dropout in the input signal gi. When a discontinuous state occurs in the phase of the signal in the input signal S3, the pulse width of the output pulse P1 from the first retriggerable monostable multivibrator RTMMI changes to that of the second retriggerable monostable multivibrator RTMM2. Set time constant T2
The second retriggerable monostable multivibrator RTMM2 has a longer time length than the above-mentioned time length T2.
Depending on the time position of the leading edge of the output pulse P1 from the first retriggerable monostable multivibrator RTMMI, the second retriggerable monostable multivibrator RTMM2 is determined only when it has not been triggered for a period longer than . The time position at which was last triggered (time t2 and time tS in the case of (d) in Fig. 4)
When the time length T1 has elapsed since then (time ta and time tb in the case of (d) in FIG. 4), the high level state changes to the low level state.

Therefore, in the pulse stretching circuit PS to which the pulse P2 shown in FIG. 4(d) output from the second retriggerable monostable multivibrator RTMM2 is supplied, the pulse P2 is at a high level. The time ta when the state changes from the state to the low level state, and the time t
4b, a pulse Po (discrimination signal) having a predetermined pulse width To is generated and sent to the output terminal 2, as shown in FIG. 4(e).

In this way, in the previously proposed signal duty cycle detection circuit shown in FIG.
As is clear from the diagrams shown in (f), the signal Si supplied to the input terminal 1 and whose duty cycle is to be detected as shown in (a) of FIG. If there is a missing part of the signal or a discontinuous part of the signal, a discrimination signal Po can be sent to the output terminal 2 in response to the missing part.

(Problems to be Solved by the Invention) In the previously proposed signal duty cycle detection circuit explained with reference to FIGS. 3 and 4, there is a missing portion of the signal, and the period of the signal Si is retriggerable. When the time constant T1 set in the monostable multivibrator RTMMI becomes longer.

and when there is a discontinuous phase part in the signal Si whose duty cycle is to be detected, and the period of the signal Si becomes shorter than the time constant T2 set in the retriggerable monostable multivibrator RTMM2. In either case, the state can be detected well and the pulse Po used as the discrimination signal can be sent out from the output terminal 2.

However, in the previously proposed signal duty cycle detection circuit, the time length of one cycle of the signal targeted for detection of the signal duty cycle exceeds a predetermined maximum value or shortest value. The first time constant value is set in advance as a fixed value as the reference time length used when determining whether or not the data has been received. Second retriggerable monostable multivibrator RTMMI, RT
Since the time constant in MM2 is used, the following problems have arisen.

That is, the first component used as a component in the previously proposed signal duty cycle detection circuit.
．． Second retriggerable monostable multivibrator RT
The time constant circuit of MMI and RTMM2 is usually composed of circuit elements such as resistors and capacitors, but the circuit constants such as resistance values and capacitance values of the circuit elements such as resistors and capacitors are well-known. It necessarily contains errors, and circuit constants inevitably change due to temperature changes and changes over time.

Therefore, as mentioned above, the standard used when determining whether the time length of one cycle of a signal whose duty cycle is being detected exceeds a predetermined maximum value or minimum value. If a time constant circuit is used in which the time length is determined by a resistance value and a capacitance value, adjustment is required to set the time constant to a predetermined fixed value.

In addition, the stability of the circuit is impaired due to changes in circuit constants due to temperature changes or changes over time.Furthermore, if the signals to be detected have different frequencies, the duty cycle of the signal should be detected. In this example, the first one is used as a component in a signal duty cycle detection circuit. Inconveniences arise, such as the need to change and readjust the circuit constant values of resistors and capacitors used in the configuration of the time constant circuits of the second retriggerable monostable multivibrators RTMMl and RTMM2. Therefore, a solution was required.

(Means for Solving the Problems) The present invention provides a signal duty cycle that generates a discrimination signal when the time length of one cycle of the signal exceeds a predetermined longest value and shortest value. a detection circuit, comprising: a limiter to which a signal targeted for duty cycle detection is supplied; The first time constant should be set to be slightly shorter than the shortest time length in the range of change in time length of one cycle of the signal under normal conditions.
a retriggerable monostable multivibrator and a normal state of a signal that is triggered at the time position of the leading edge of the output pulse from the first retriggerable monostable multivibrator and is subject to duty cycle detection. a second retriggerable monostable multivibrator whose time constant should be set to a time constant slightly longer than the longest time length in the change range of the time length of one cycle of the signal; and the output of the second retriggerable monostable multivibrator. A signal duty cycle detection circuit comprising a pulse expansion circuit that generates an output pulse of a predetermined pulse width from the time position of the trailing edge of the pulse. As the second retriggerable monostable multivibrator, one each composed of a trigger circuit, a lamp voltage generation circuit, and a voltage comparator to which a predetermined reference voltage is applied is used,
Further, means for supplying the output pulse of the first retriggerable monostable multivibrator as a comparison signal to an error amplifier to which a predetermined reference voltage is applied via an integrating circuit; The first point mentioned above. Means for supplying a comparison voltage to each voltage comparator in the second retriggerable monostable multivibrator, and an average of the signals whose duty cycles are detected by the first retriggerable monostable multivibrator. means for generating an output pulse having a pulse width shorter by a predetermined ratio compared to the average period of the signal whose duty cycle is to be detected in accordance with the average period of the signal. , the above-mentioned second retriggerable monostable multivibrator follows the average period of the signal whose duty cycle is to be detected, and detects the average period of the signal whose duty cycle is to be detected. and means for generating and sustaining an output pulse having a pulse width that is longer by a predetermined ratio than the period.

(Example) Hereinafter, specific contents of the signal duty cycle detection circuit of the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of a signal duty cycle detection circuit according to the present invention. In FIG. 1, 1 indicates a signal Si (for example, frequency modulated Furthermore, LMIT is a limiter, and RTMMla is the target of duty cycle detection when triggered at the time position of the leading edge of the output pulse PQ from the limiter LMIT described above. Following the average period of the signal,
A first retriggerable monostable configured to generate an output pulse P1a having a pulse width shorter by a predetermined ratio than the average period of the signal whose duty cycle is being detected. The RTMM2a is a multivibrator, and is further subjected to duty cycle detection when triggered at the time position of the leading edge of the output pulse Pla of the first retriggerable monostable multivibrator RTMMla. generates an output pulse P2a having a pulse width that is longer by a predetermined ratio than the average period of the signal whose duty cycle is being detected. A second retriggerable monostable multivibrator configured as follows, the first retriggerable monostable multivibrator RTMM1a has a trigger circuit TRCl and a lamp voltage generation circuit REGI.
and a voltage comparator COMP to which the reference voltage Vs is applied.
The second retriggerable monostable multivibrator RTMM2a includes a trigger circuit TRC2 and a lamp voltage generation circuit REG2.
and a voltage comparator COMP to which the reference voltage Vs is applied.
2.

In FIG. 1, PS is a pulse expansion circuit (for example, , a monostable multivibrator), and the output pulse Po from this pulse expansion circuit PS is sent to the output terminal 2.

The aforementioned voltage comparator G provided in the aforementioned first retriggerable monostable multivibrator RTMM1a.
The reference voltage Vs supplied to OMPI and the second retriggerable monostable multivibrator RTMM2a described above
The reference voltage Vs supplied to the voltage comparator GOMP2 is the voltage Vin obtained by integrating the output pulse Pla of the first retriggerable monostable multivibrator RTMM1a by the integrating circuit INTC.
The output voltage Vs from the error amplifier EA which is amplified and outputted from the voltage difference between t and a predetermined reference voltage Vraf is used.

The operation of the signal duty cycle detection circuit of the present invention shown in FIG. 1 and configured as described above will be explained as follows with reference to the waveform diagram shown in FIG. 2.

The signal Si whose duty cycle is to be detected through the input terminal 1 to the limiter LMIT in the signal duty cycle detection circuit of the present invention shown in FIG. When the limiter LMIT to which the input signal Si was supplied outputs an output pulse Pn (as shown in FIG. 2), which corresponds to the signal Si supplied to it, (see (a)) is output.

(a
) When a pulse PQ as shown in FIG. (
A narrow trigger pulse Pt1 as shown in b) is generated and supplied to the ramp voltage generation circuit REGI.

The lamp voltage generation circuit REGI generates a lamp voltage Vrl as shown in FIG.
and supplies it to the voltage comparator COMPI.

As mentioned above, the voltage comparator GOMPI has the first
Retriggerable monostable multivibrator RTMM1
An output voltage V from an error amplifier EA that amplifies and outputs the voltage difference between the voltage Vint obtained by integrating the output pulse Pla of a by the integrating circuit INTC and a predetermined reference voltage Vref.
s is supplied as a reference voltage V s (indicated by a dashed line in FIG.
During the period in which the voltage exceeds the reference voltage Vs, the voltage becomes a low level voltage va, and the output voltage V from the integrating circuit INTC
The output pulse Pla of the high-level period has a pulse width Tla such that int becomes the high-level voltage vh during a period in which int is lower than the reference voltage Vs, that is, the output pulse Pla of the first retriggerable monostable multivibrator RTMM1a. (see (d) in FIG. 2) and supplies it to the second retriggerable monostable multivibrator RTMM2a and the integrating circuit INTC as described above.

Now, the output voltage Vint ((d) in FIG. 2) from the integrating circuit I NTC that integrates the output pulse Pla (see (d) in FIG. 2) of the first retriggerable monostable multivibrator RT M ) shown by a dotted line in ) corresponds to the average voltage during one period of the output pulse Pin of the first retriggerable monostable multivibrator RTMM1a, but as described above, Retriggerable monostable multivibrator RT
High level period T of output pulse Pla of M M la
Assuming that la is a high-level voltage yh, a low-level period is a low-level voltage va, and one period of the signal whose duty cycle is to be detected is τ0, then the integral The output voltage Vint (indicated by a dotted line in FIG. 2(d)) from the circuit INTC is expressed by the following equation (1).

Vint=(Tla/1o)(Vh-VQ)+V
Q-(1) By the way, the output voltage Vint of the above-mentioned integrating circuit INTC is compared with a predetermined reference voltage Vref set therein in the error amplifier EA.

The output voltage Vs of the error amplifier EA is used to generate the output voltage Vs of the error amplifier EA, and as described above, the output voltage Vs of the error amplifier EA is the voltage comparator GOMPI in the first retriggerable monostable multivibrator RT M M la. Since it is supplied as the reference voltage Vs, the voltage comparator COMPI-h integrator circuit INTC-4 in the first retriggerable monostable multivibrator RTMM1a
Error amplifier EA → voltage comparator C in the first retriggerable monostable multivibrator RT M M 1 a
Due to the operation of a negative feedback loop such as OMPI→, the voltage value of the output voltage Vint of the above-mentioned integrating circuit INTC is as follows.

As shown in the following equation (2), the voltage value is approximately equal to the predetermined reference voltage Vref value set in the error amplifier EA.

V in t″: V r a f − (2) So,
The output pulse Pla(
The pulse width Tla in FIG. 2(d)) is expressed by the first-order equation (3) from the equations (1) and (2) described above.

Tla=to(Vref-Vll)/(Vh-VQ)-
(3) As is clear from the above equation (3), the above-mentioned first retriggerable monostable multivibrator RTMM
The pulse width Tla of the output pulse 1a Pla is equal to the predetermined reference voltage Vref set in the error amplifier EA.
The voltage value can be set at a constant ratio to the average period τ0 of the signal S1 whose duty cycle is to be detected via the input terminal 1.

Next, the second retriggerable monostable multivibrator RTMM2a, to which the output pulse Pla of the first retriggerable monostable multivibrator RTMMla described above is supplied as a trigger pulse, has its trigger circuit TRC2 Output pulse Pl of the retriggerable monostable multivibrator RT M M la
(e) in Fig. 2, which rises at each time position of the leading edge at a.
A narrow trigger pulse Pt2 as shown in FIG. 1 is generated and supplied to the ramp voltage generation circuit REG2.

The above-mentioned ramp voltage generation circuit REG2 generates a ramp voltage Vr2 as shown in FIG. It is supplied to voltage comparator GOMP2. The second retriggerable monostable multivibrator RT M M 2a has an average period τ of the signal Si whose duty cycle is to be detected via the input terminal 1.
so that an output pulse P2a with a pulse width T2a longer than 0 can be generated.

The time constant is set large, and the slope of the output voltage Vr2 generated from the lamp voltage generating circuit REG2 on the time axis is gentle.

Therefore, for example, after the output pulse Pla of the first retriggerable monostable multivibrator RTMM1a generated at time t1 in FIG. 2, the output pulse Pla to be generated from the first retriggerable monostable multivibrator RTMM1a at time t3 is , assuming that there is no such thing, the output voltage Vr2 generated from the lamp voltage generation circuit REG2 in this case is as shown by the straight line shown by the solid line in (f) of FIG. 2 from time t1 to time t3. Keep changing.

After time t3, the change continues as shown by the broken line in FIG. It shows the change mode that returns to the level.

For the voltage comparison @COMP2 mentioned above, as mentioned above, the first
Retriggerable monostable multivibrator RTMM1
A voltage Vint, which is obtained by integrating the output pulse Pla of a by an integrating circuit INTC, is supplied as a comparison signal, and an output voltage Vs from an error amplifier EA that amplifies and outputs the voltage difference from a predetermined reference voltage V ref is supplied as a comparison signal. Since it is supplied as the reference voltage V s (indicated by a dashed line in FIG. 2(f)), the output pulse P2a of the voltage comparator COMP2 described above is generated from the lamp voltage generation circuit REG2. The output voltage Vr2 remains at a high level voltage vh until it exceeds the reference voltage Vs.

Therefore, as in the above example, 1, for example, time t in FIG.
Next to the output pulse Pla of the first retriggerable monostable multivibrator RTMM1a generated at time t3
The first retriggerable monostable multivibrator RT
M! Considering the case where there is no output pulse Pla to be generated from vHa, the output voltage Vr generated from the lamp voltage generation circuit REG2 in such a case
2 changes as shown by the solid line in (f) of FIG. 2 from time tl to time t3, and changes as shown by the broken line in (f) of FIG. 2 after time t3. I'm going to do it, but
At time t4 after time t3, when the output voltage Vr2 generated from the ramp voltage generation circuit REG2 exceeds the reference voltage Vs supplied to the voltage comparator GOMP2, the output pulse Pea of the voltage comparator GOMP2, That is, the output pulse Pea generated from the second retriggerable monostable multivibrator RT M M 2a
However, as illustrated by the broken line in (g) of FIG. 2, the voltage vh in the high level state changes from the voltage v in the low level state.
Changes to Q.

Then, the output pulse P2a from the second retriggerable monostable multivibrator RT M M 2a described above
changes from a high level state to a low level state, that is, the time position of the trailing edge of the output pulse P2a of the second retriggerable monostable multivibrator RTMM2a (in the case illustrated in FIG. 2(g), the time t4) from a pulse stretching circuit PS (for example, a monostable multivibrator) with a predetermined pulse width To (in the case illustrated in FIG. 2 (g), the pulse width from time t4 to time t7) (discrimination). signal) is generated and sent to output terminal 2.

By the way, during the period from time tl to time t4 described above, the second retriggerable monostable multivibrator RT
This corresponds to the time constant set in MM2a, but it is clear from the explanation of the operation above that the above time length changes depending on the reference voltage v3 supplied to the voltage comparator GOMP2. It is.

Here, the pulse width Tea of the output pulse P2a of the second retriggerable monostable multivibrator RT M M 2a is equal to the average period τ0 of the signal Si whose duty cycle is detected via the input terminal 1. We will explain what is done at a certain ratio to .

As is well known, the pulse width of the output pulse from a monostable multivibrator is generally proportional to 1 time constant, so now,
First retriggerable monostable multivibrator RT
The time constant of M M la is (CIXRI).

The pulse width of the output pulse Pla is Tla, and the second
Retriggerable monostable multivibrator RT M
The time constant of M2a is (C2XR2), the output pulse P2a
Let T2a be the pulse width of
There is a relationship R2).

Therefore, from the above relationship, the pulse width T2a of the second retriggerable monostable multivibrator RTMM2a is expressed by the following equation (4).

T2a=T1a(C2/C1)(R2/R1)-(4)
The pulse width T2a of the second retriggerable monostable multivibrator RTMM2a is as follows.

From the already mentioned equations (3) and (4), it is expressed by the first-order equation (5).

T2a=to(Vref-VQ)/(Vh-V
Q))(C2/C1)・(R2/R1)・・・・・・
(5) As is clear from the above equation (5), the second retriggerable monostable multivibrator RT M M
The pulse width T2a of the output pulse P2a of 2a is equal to the predetermined reference voltage V re set in the error amplifier EA.
The voltage value of f and the first. By setting the circuit constants of the circuit elements such as the resistors R1 and R2 of the time constant circuit and the capacitors CI and C2 in the second retriggerable monostable multivibrator RTMM1a and RTMM2a as required, the duty can be controlled via the input terminal 1. It can be a constant ratio to the average period τ0 of the signal SL whose cycle is to be detected.

(Effects of the Invention) As is clear from the above detailed explanation, the signal duty cycle detection circuit of the present invention allows the time length of one cycle of the signal to exceed the predetermined longest and shortest values. a signal duty cycle detection circuit configured to generate a discrimination signal when a signal is detected, the limiter being supplied with a signal whose duty cycle is to be detected;
1 of the signal in the normal state of the fFI signal which is triggered at the time position of the leading edge of the output pulse from the limiter described above and whose duty cycle is detected.
A first retriggerable monostable multivibrator whose time constant should be set to a time constant slightly shorter than the shortest time length in the period time length change range, and a predetermined time constant in the output pulse from the first retriggerable monostable multivibrator. It is triggered at the time position of the edge and has a time constant slightly longer than the longest time length in the range of change in time length of one cycle of the signal in the normal state of the signal targeted for duty cycle detection. a second retriggerable monostable multivibrator to be set, and a pulse stretching circuit that generates an output pulse of a predetermined pulse width from the time position of the trailing edge of the output pulse of the second retriggerable monostable multivibrator. In the detection circuit for the duty cycle of a signal, each of the first and second retriggerable monostable multivibrators has a trigger circuit, a lamp voltage generation circuit, and a voltage to which a predetermined reference voltage is applied. In addition, the output pulse of the first retriggerable monostable multivibrator is supplied as a comparison signal to an error amplifier to which a predetermined reference voltage is applied via an integrating circuit. and a means for converting the output of the error amplifier described above into the first one described above. means for supplying a comparison voltage to each voltage comparator in the second retriggerable monostable multivibrator;
The first retriggerable monostable multivibrator described above follows the average period of the signal whose duty cycle is to be detected, and detects the average period of the signal whose duty cycle is to be detected. means for generating an output pulse having a pulse width shorter by a predetermined ratio compared to the second retriggerable monostable multivibrator; Means for generating and sustaining an output pulse whose pulse width is longer by a predetermined ratio compared to the average period of the signal whose duty cycle is to be detected, in accordance with the average period. Therefore, in the signal duty cycle detection circuit of the present invention, the first . Each of the pulse widths of the output pulses of the second retriggerable monostable multivibrator is determined by the average period τ0 of the signal Si supplied to the input terminal 1 and whose duty cycle is to be detected.
The above-mentioned 1. Since the output pulse width of the second retriggerable monostable multivibrator is set to the upper and lower limits of the period of the signal whose duty cycle is being detected, the circuit constants of the circuit components change. Also, as is clear from equations (3) and (5) mentioned above, the detection accuracy does not deteriorate even when the reference voltage set to the error amplifier and the first . Second
By determining the resistance ratio of the resistor and the capacitance ratio of the capacitor that make up the time constant circuit that determine the time constant of the retriggerable monostable multivibrator, it is possible to accurately set the upper and lower limits of the pulse width. In addition, even if the frequency of the signal whose duty cycle is to be detected is changed, the duty cycle detection operation can be performed without any problem. According to the circuit of the present invention, the conventional circuit described above can perform the duty cycle detection operation without any problem. This problem can be solved satisfactorily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the signal duty cycle detection circuit of the present invention, and FIG. 2 is a block diagram for explaining the operation of the signal duty cycle detection circuit of the present invention shown in FIG. Waveform diagram; FIG. 3 is a block diagram of the previously proposed signal duty cycle detection circuit; FIG. 4 is a waveform diagram for explaining the operation of the previously proposed signal duty cycle detection circuit shown in FIG. , is. 1... Input terminal of signal Si whose duty cycle is to be detected, 2... Output terminal, LMIT-.
- Limiter, RTMMI, RTMMla - first retriggerable monostable multivibrator, RTMM2. RT
MM2a...Second retriggerable monostable multivibrator, PS...Pulse expansion circuit that generates an output pulse Po (discrimination signal) with a predetermined pulse width TO, TRCl
, TRC2...Trigger circuit, REGl, REG2...
・Lamp voltage generation circuit, GOMPI. GOMP2...voltage comparator, INTC...integrator circuit, EA...error amplifier,

Claims (1)

[Scope of Claims] A signal duty cycle detection circuit that generates a discrimination signal when the time length of one cycle of the signal exceeds a predetermined longest value and shortest value, a limiter to which the signal targeted for detection is supplied, and a normal state of the signal triggered at the time position of the leading edge of the output pulse from said limiter and targeted for duty cycle detection; A first retriggerable monostable multivibrator whose time constant should be set to a slightly shorter time length than the shortest time length in the range of change in the time length of one cycle of the signal; triggered at the time position of the leading edge in the output pulse, and
A second retriggerable monostable multifunction device whose time constant should be set to be slightly longer than the longest time length in the change range of the time length of one cycle of the signal whose duty cycle is being detected in a normal state. A signal duty cycle detection circuit comprising a vibrator and a pulse expansion circuit that generates an output pulse of a predetermined pulse width from the time position of the trailing edge of the output pulse of the second retriggerable monostable multivibrator, The first and second retriggerable monostable multivibrators described above are each configured by a trigger circuit, a lamp voltage generation circuit, and a voltage comparator to which a predetermined reference voltage is applied, Further, means for supplying the output pulse of the first retriggerable monostable multivibrator as a comparison signal to an error amplifier to which a predetermined reference voltage is applied via an integrating circuit; The above-mentioned first and second
Means for supplying as a comparison voltage to each voltage comparator in the retriggerable monostable multivibrator, and the average period of the signal whose duty cycle is detected by the first retriggerable monostable multivibrator. means for generating an output pulse having a pulse width shorter by a predetermined ratio compared to the average period of the signal whose duty cycle is being detected; The second retriggerable monostable multivibrator tracks the average period of the signal whose duty cycle is being detected, and has a predetermined value compared to the average period of the signal whose duty cycle is being detected. Means for generating output pulses with a pulse width longer than a predetermined ratio■■■■■■Skull M duty cycle detection circuit