JP2006105900A - Sensor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sensor circuit capable of preventing occurrence of a delay, when detecting an abnormality of an offset voltage. <P>SOLUTION: An abnormality detection circuit 40 has a constitution equipped with a peak hold circuit 41 and a bottom hold circuit 42, and an abnormality of the offset voltage is detected, based on a voltage determined by adding the maximum voltage Vmax held by the peak hold circuit 41 and the minimum voltage Vmin held by the bottom hold circuit 42 together. Hereby, the abnormality of the offset voltage can be detected. Since a restriction that a time constant of LPF is required to be enlarged as before becomes unnecessary by this constitution, occurrence of a delay can be prevented, when detecting the abnormality of the offset voltage, and this sensor circuit capable of detecting a temporary abnormality of the offset voltage converging within a time constant can be provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a sensor circuit that can detect an abnormality of an offset voltage.

  Conventionally, a sensor device including a pair of left and right vibrators such as a gyro sensor is known. In a sensor circuit used in such a sensor device, for example, after each detection signal of each vibrator is voltage-converted by a charge amplifier, a differential output of each detection signal after voltage conversion is performed by a differential amplifier circuit. After that, the sensor output is used after passing through a synchronous detection circuit, a low-pass filter (hereinafter referred to as LPF) and a zero / sensitivity temperature characteristic adjustment circuit.

  In such a sensor circuit, the differential output in the differential amplifier circuit is set to a predetermined value according to the application of the sensor device, etc., but the offset voltage of this differential output is abnormal There is a case. For example, the offset voltage becomes abnormal when a bonding wire that electrically connects the vibrator and the charge amplifier is disconnected.

  For this reason, it has been proposed that the sensor circuit includes an abnormality detection circuit that detects that the offset voltage is abnormal based on the differential output. Specifically, this circuit has a circuit configuration as shown in FIG. In FIG. 6, an input signal indicates a differential output of the above-described differential amplifier circuit, and is an AC signal.

As shown in this figure, after the input signal is input to the LPF 100, the signal after passing through the LPF 100 is input to the window comparator 101, and is compared with the upper limit threshold value VRH and the lower limit threshold value VRL. It has become. If the signal after passing through the LPF is within the range between the upper threshold value VRH and the lower threshold value VRL, the diagnostic signal is not output, and when the signal is out of the range, the diagnostic signal is output. (For example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 08-077714

  However, in the conventional sensor circuit, since the differential output as an AC signal is smoothed by the LPF, the time constant of the LPF must be sufficiently increased. For this reason, it has been found that there is a problem that a delay occurs until an offset voltage abnormality is detected, and a problem that a temporary offset voltage abnormality that converges within a time constant cannot be detected. These problems will be described in detail with reference to FIGS.

  FIGS. 7 and 8 both show in detail the circuit configuration of the abnormality detection circuit provided in the conventional sensor circuit shown in FIG. 6, and FIG. 7 shows the circuit configuration of the non-inverted LPF. FIG. 8 shows a circuit configuration of an inversion type LPF.

  When the amplitude of the input signal is Va, the DC component is Vdc, the frequency is fd, and the angular frequency is ωd, the angular frequency ωd is expressed by the following equation.

(Equation 1)
ωd = 2 · π · fd Formula (1)
Therefore, the input signal VIN can be expressed by the following equation.

(Equation 2)
VIN (t) = Va · sin (ωd · t) + Vdc (2)
The DC component of the input signal here is used for detecting an abnormality of the offset voltage. 7 and 8, if the output voltage of the LPF is VLPF and the voltage used as the reference voltage of the LPF in FIG. 8 is VREF (generally, VREF = VCC / 2 is used), the LPF is non-inverted. In the case of the type and the case of the inverted type, the VLPF is indicated as follows in each case.

For non-inverted type:
(Equation 3)
VLPF = Vdc (3)
For reverse type:
(Equation 4)
VLPF = 2 · VREF−Vdc Equation (4)
These voltages are input to the window comparator 101, and are compared with the voltage VRL and a voltage VRH higher than this voltage by the two comparators 101a and 101b provided in the window comparator 101, respectively. The comparator 101b outputs a low level when the VLPF is lower than the voltage VRL, and the comparator 101a outputs a low level when the VLPF is higher than the voltage VRL. For this reason, when either one of the comparators 101a and 101b is at a low level, a low level is output from the AND circuit 101c to be a diagnosis signal. The voltage VRL and the voltage VRH are formed by dividing the power supply voltage VCC by the voltage dividing resistors 101d to 101f provided in the window comparator 101.

  That is, the VLPF with respect to the input signal in FIGS. 5 and 6 is shown in FIG. 7, and the difference ΔVdc between VLPF and VREF is within the range of voltages VRL to VRH (normal voltage range) set around VREF. It is determined whether or not it is present.

  In such an abnormality detection circuit, it is desirable to reduce the ripple (fd component) remaining after smoothing. Further, the cut-off frequency fc of the LPF 100 needs to be sufficiently smaller than the frequency fd of the input signal. For this reason, the time constant of the LPF 100 has to be increased, a delay occurs until an offset voltage abnormality is detected, and a temporary offset voltage abnormality that converges within a short time within the time constant is detected. It will not be possible.

  In view of the above, it is a first object of the present invention to provide a sensor circuit that can prevent a delay from occurring when an abnormality of an offset voltage is detected. Another object of the present invention is to provide a sensor circuit capable of detecting a temporary offset voltage abnormality that converges in a short time.

  In order to achieve the above object, according to the first aspect of the present invention, the peak hold for holding the maximum voltage (Vmax) of the input signal every predetermined sampling period using the output of the differential amplifying means (33) as the input signal. Means (41), bottom hold means (42) for holding the minimum voltage (Vmin) of the input signal at every predetermined sampling period, and maximum voltage (Vmax) and bottom hold held by the peak hold means (41). An adding means (43) for outputting a voltage obtained by adding the minimum voltage (Vmin) held in the means (42), and a voltage output from the adding means (43) is an upper threshold (VRH) and a lower limit threshold. An abnormality detection circuit (40) having a determination means (43) for detecting an abnormality of the offset voltage depending on whether or not the value is in a range between the values (VRL). It is characterized in that they are gills.

  As described above, the abnormality detection circuit (40) includes the peak hold means (41) and the bottom hold means (42). Then, an abnormality of the offset voltage is detected based on a voltage obtained by adding the maximum voltage (Vmax) held by the peak hold means (41) and the minimum voltage (Vmin) held by the bottom hold means (42). I am doing so.

  As a result, even if the input signal offset voltage gradually changes or the input signal offset voltage becomes instantaneously abnormal, it can be detected and a diagnostic signal output. It becomes possible.

  In this way, it is possible to detect an abnormality in the offset voltage. According to such a configuration, since there is no restriction such as the need to increase the time constant of the LPF as in the prior art, it is possible to prevent a delay from occurring when detecting an offset voltage abnormality. Thus, it is possible to provide a sensor circuit that can detect a temporary offset voltage abnormality that converges in a short time.

  In this case, as set forth in claim 2, the predetermined sampling period is set to be longer than the period of the input signal to be an AC signal. For example, as described in claim 3, the predetermined sampling period is set to a multiple of the period of the input signal.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a block configuration of a sensor circuit including an abnormality detection apparatus to which an embodiment of the present invention is applied. Hereinafter, the sensor circuit according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, a vibrator 10, a drive circuit 20, a yaw detection circuit 30, and an abnormality detection circuit 40 are provided, and a sensor circuit is configured by these.

  The vibrator 10 corresponds to a sensing means, and includes a sensor element (not shown) for driving and detecting yaw, and when yaw is generated when the driving sensor element is performing driving vibration. The sensor element for detection composed of a pair is vibrated by the Coriolis force. The vibrator 10 generates outputs (first and second detection signals) corresponding to vibrations in each of the pair of detection sensor elements, and detects whether the drive sensor element is accurately driven and vibrated. Therefore, an output corresponding to the drive vibration is generated.

  The drive circuit 20 is for vibrating the drive sensor element in the vibrator 10. The drive circuit 20 includes a booster circuit 21 including a sensor drive power supply, a charge amplifier 22, a phase shifter 23, and a constant amplitude control unit 24.

  The booster circuit 21 forms a voltage for oscillating the driving sensor element in the vibrator 10 by boosting the voltage from the sensor driving power source, and drives the driving sensor element with a predetermined amplitude and a predetermined frequency. For this purpose, the voltage generated by the sensor drive power supply is boosted, and a voltage having a predetermined frequency is output as a drive signal to the drive sensor element. Specifically, the drive signal generated by the booster circuit 21 is adjusted based on the drive signal fed back via the charge amplifier 22 and the signal from the constant amplitude control unit 24.

  The charge amplifier 22 receives a detection signal (hereinafter referred to as a drive vibration detection signal) corresponding to the drive vibration of the driving sensor element in the vibrator 10 from the vibrator 10 and converts the voltage into a detection signal. A drive vibration detection signal after voltage conversion by the charge amplifier 22 is input to the booster circuit 21, the constant amplitude control unit 24, and the phase shifter 23.

  The phase shifter 23 is for adjusting the phase of the drive signal. As described above, since the drive signal is formed by the booster circuit 21 based on the drive vibration detection signal, the phase of the drive vibration detection signal is shifted from the phase of the drive signal that is actually desired to be output to the drive sensor element. Yes. In order to repair this phase shift, the phase of the drive vibration detection signal must be adjusted to match the phase of the drive signal. For this reason, the phase of the drive vibration detection signal is corrected by the phase shifter 23, and as a result, the phase of the drive signal formed based on this is adjusted. Thereby, the frequency of the drive signal is set to fd.

  The constant amplitude control unit 24 detects the current amplitude of the sensor element for driving from the driving vibration detection signal, and outputs a signal for correcting the amplitude to be constant to the booster circuit 21.

  The yaw detection circuit 30 is for obtaining a sensor output based on the detection signal of the vibrator 10. The yaw detection circuit 30 includes two charge amplifiers 31 and 32, a differential amplifier circuit 33, a synchronous detection circuit 34, an LPF 35, and a zero point / sensitivity temperature special adjustment circuit 36.

  The two charge amplifiers 31 and 32 receive a detection signal (hereinafter referred to as a yaw detection signal) corresponding to vibration generated when yaw is applied to the detection sensor element from each of the pair of vibrators 10. Are converted to voltages, which respectively correspond to first and second voltage conversion means. The yaw detection signal after voltage conversion by each of these charge amplifiers is input to the differential amplifier circuit 33.

  The differential amplifier circuit 33 corresponds to a differential amplifier that generates a differential output of a yaw detection signal whose voltage has been changed by the charge amplifiers 31 and 32. The differential output of the differential amplifier circuit 33 is input to the synchronous detection circuit 34 and used as an input signal in the abnormality detection circuit 40. The differential output of the differential amplifier circuit 33 becomes an AC signal including a predetermined offset voltage that becomes a DC component.

  The synchronous detection circuit 34 passes a component synchronized with the frequency fd from the differential output of the differential amplifier circuit 33 based on the phase adjusted by the phase shifter 23, and outputs it to the LPF 35.

  The LPF 35 extracts only components having a predetermined frequency or less from the signal after passing through the synchronous detection circuit 34.

  The zero point / sensitivity temperature special adjustment circuit 36 adjusts the signal after passing through the LPF 35 because the output offset and sensitivity temperature characteristics are also included. The signal after being adjusted by the special adjustment circuit 36 is used as a sensor output.

  The abnormality detection circuit 40 is for detecting an abnormality in the offset voltage. The abnormality detection circuit 40 includes a peak hold circuit 41, a bottom hold circuit 42, an adder 43, and a window comparator 44.

  The peak hold circuit 41 holds the maximum voltage Vmax as the peak value of the input signal expressed as an AC signal, and corresponds to a peak hold means. The sampling frequency in the peak hold circuit 41 is at least lower than the frequency of the input signal (more precisely, the frequency of the AC signal of the input signal), that is, the sampling period (sampling interval) is longer than one period of the input signal. Is set. In the present embodiment, the sampling frequency of the peak hold circuit 41 is set to ¼ Fd with respect to the frequency Fd of the input signal, and the peak voltage 41 is held by the peak hold circuit 41 during the four cycles of the input signal. It has become.

  The bottom hold circuit 42 holds the minimum voltage Vmin as the bottom value of the input signal expressed as an AC signal, and corresponds to bottom hold means. The sampling frequency in the bottom hold circuit 42 is set to be lower than at least the frequency of the input signal (more precisely, the frequency of the AC signal of the input signal), that is, the sampling cycle is longer than one cycle of the input signal. . In the present embodiment, the sampling frequency of the bottom hold circuit 42 is set to 1/4 Fd with respect to the frequency Fd of the input signal, and the minimum voltage Vmin in the four cycles of the input signal is held by the bottom hold circuit 42. It has become. The sampling period in the bottom hold circuit 42 has the same value as the sampling period in the peak hold circuit 41 described above, and the sampling period is also synchronized with the peak hold circuit 41.

  The adder 43 adds the maximum voltage Vmax held by the peak hold circuit 41 and the minimum voltage Vmin held by the bottom hold circuit 42, and corresponds to addition means.

  The window comparator 44 is used as a determination unit that compares the differential output of the differential output circuit 42, that is, the DC component of the input signal, with the upper limit threshold value VRH and the lower limit threshold value VRL. If the DC component of the input signal is in the range between the upper threshold value VRH and the lower threshold value VRL, the diagnostic signal is not output from the window comparator 44, and if it is out of the range, the window comparator 44 is output. A diagnostic signal is output from

  FIG. 2 shows an example of a specific circuit configuration of the abnormality detection circuit in the sensor circuit configured as described above.

  As shown in this figure, the peak hold circuit 41 has an operational amplifier 41a, a capacitor 41b, a switch 41c, and a diode 41d. An input signal is input to the non-inverting input terminal of the operational amplifier 41a, and the anode of the diode 41d is connected to the output terminal of the operational amplifier 41a. Further, the cathode of the diode 41d and the inverting input terminal of the operational amplifier 41a are connected, and a capacitor 41b and a switch 41c are connected between the cathode of the diode 41d and GND so as to be connected in parallel to each other.

  In the peak hold circuit 41 configured as described above, the switch 41c is turned off during the sampling period, and the switch 41c is driven to the on state every sampling cycle. During the sampling period, since the diode 41d is connected in the forward direction with respect to the output terminal of the operational amplifier 41a, feedback is also provided when the output terminal of the operational amplifier 41a reaches the highest voltage. For this reason, the capacitor 41b is charged with the maximum voltage Vmax during the sampling period. When one sampling period, that is, the sampling period ends, the switch 41c is turned on, and the voltage charged in the capacitor 41b is refreshed.

  The bottom hold circuit 42 includes an operational amplifier 42a, a capacitor 42b, a switch 42c, and a diode 42d. An input signal is inputted to the non-inverting input terminal of the operational amplifier 42a, and the cathode of the diode 42d is connected to the output terminal of the operational amplifier 42a. Further, the anode of the diode 42d and the inverting input terminal of the operational amplifier 42a are connected, and further, the capacitor 42b and the switch 42c are connected between the anode of the diode 42d and GND so as to be connected in parallel to each other.

  The bottom hold circuit 42 configured in this manner basically performs the same operation as the peak hold circuit 41. However, since the diode 42d is connected in the reverse direction with respect to the output terminal of the operational amplifier 42a, feedback is performed only when the output terminal of the operational amplifier 42a has the lowest voltage. Therefore, the capacitor 42b is charged with the minimum voltage Vmin during the sampling period. When one sampling period, that is, the sampling period ends, the switch 42c is turned on, and the voltage charged in the capacitor 42b is refreshed.

  The output voltages of the peak hold circuit 41 and the bottom hold circuit 42 are input to the adder 43 through the emitter follower circuits 45 and 46. The emitter follower circuits 45 and 46 function as simple buffers.

  The adder 43 includes an operational amplifier 43a, a resistor 43b connected between the inverting input terminal of the operational amplifier 43a and the output terminal of the emitter follower circuit 45, and an output terminal of the emitter follower circuit 46 and the inverting input terminal of the operational amplifier 43a. The resistor 43c is connected, and the resistor 43d is connected between the inverting input terminal and the output terminal of the operational amplifier 43a.

  The adder 43 configured as described above adds the output voltages of the peak hold circuit 41 and the bottom hold circuit 42, that is, the maximum voltage Vmax and the minimum voltage Vmin, and outputs the added voltage. . Hereinafter, the output of the adder 43 is referred to as an abnormality detection signal.

  The window comparator 44 includes three voltage dividing resistors 44a to 44c that divide the power supply voltage VCC into an upper limit threshold value VRH and a lower limit threshold value VRL, two comparators 44d and 44e, and an AND circuit 44f. Has been.

  In the window comparator 44 configured in this way, the two comparators 44d and 44e compare with the voltage VRL and the voltage VRH, respectively. The comparator 44e outputs a low level when the voltage of the abnormality detection signal is lower than the voltage VRL, and the comparator 44d outputs a low level when the voltage of the abnormality detection signal is higher than the voltage VRL. . For this reason, when the output of either one of the comparators 44d and 44e becomes a low level, a low level is output from the AND circuit 44f to be a diagnosis signal.

  Next, the operation of the sensor circuit configured as described above will be described. Of the sensor circuits shown in the present embodiment, the parts other than the abnormality detection circuit 40 are conventionally used, and therefore, here, an abnormality is described. Only the operation of the detection circuit 40 will be described.

  First, when the differential output of the differential amplifier circuit 33 in the yaw detection circuit 30 is generated, it is input to the peak hold circuit 41 and the bottom hold circuit 42 as input signals. The peak hold circuit 41 outputs the maximum voltage Vmax, and the bottom hold circuit 42 outputs the minimum voltage Vmin. Then, the maximum voltage Vmax and the minimum voltage Vmin are added by the adder 43, and a voltage corresponding to that is output.

  The maximum voltage Vmax and the minimum voltage Vmin at this time and the voltage obtained by adding them will be described with reference to the normal state in which no abnormality has occurred in the offset voltage and the input signal waveforms in the abnormal state in which the abnormality has occurred.

  FIG. 3 shows an input signal waveform in a normal state where no abnormality occurs in the offset voltage. FIG. 3A shows a case where yaw has not occurred, and FIG. 3B shows a case where yaw has occurred. Each is shown. FIG. 4 shows an input signal waveform when an abnormality occurs such that the offset voltage gradually changes, and FIG. 5 shows an input signal waveform when the offset voltage becomes abnormal abnormally. .

  As shown in FIG. 3A, when the offset voltage of the input signal is not abnormal, the maximum voltage Vmax and the minimum voltage Vmin are voltages having the same width Va around the reference voltage VREF. The same can be said when the yaw is generated, although the values of the maximum voltage Vmax and the minimum voltage Vmin fluctuate with respect to the case where the yaw is not generated.

  Therefore, the relationship of the following equation is established, and when the maximum voltage Vmax and the minimum voltage Vmin are added, a constant voltage (2 × VREF) is indicated.

(Equation 5)
VREF = (Vmax + Vmin) / 2 Formula (5)
On the other hand, when an abnormality occurs in the offset voltage, the center of the input signal gradually changes from VREF to VREF2 as shown in FIG. 4, or an AC waveform is obtained as shown in FIG. The expected input signal is momentarily distorted.

  In these cases, the sum of the maximum voltage Vmax and the minimum voltage Vmin does not become the constant voltage. Specifically, in the case shown in FIG. 4, a voltage obtained by adding the maximum voltage Vmax and the minimum voltage Vmin is between VREF and VREF2. In the case shown in FIG. 5, the sum of the maximum voltage Vmax and the minimum voltage Vmin is greater than VREF.

  Then, a voltage obtained by adding the maximum voltage Vmax and the minimum voltage Vmin by the adder 43 is input to the window comparator 44, and this voltage is set in a range of voltages VRL to VRH centered on VREF (normal voltage range). It is determined whether or not it is inside.

  As described above, in the present embodiment, the abnormality detection circuit 40 is configured to include the peak hold circuit 41 and the bottom hold circuit 42. An abnormality of the offset voltage is detected based on a voltage obtained by adding the maximum voltage Vmax held by the peak hold circuit 41 and the minimum voltage Vmin held by the bottom hold circuit 42.

  As a result, even if the input signal offset voltage gradually changes or the input signal offset voltage becomes instantaneously abnormal, it can be detected and a diagnostic signal output. It becomes possible.

  In this way, it is possible to detect an abnormality in the offset voltage. According to such a configuration, since there is no restriction such as the need to increase the time constant of the LPF as in the prior art, it is possible to prevent a delay from occurring when detecting an offset voltage abnormality. Thus, it is possible to provide a sensor circuit capable of detecting a temporary offset voltage abnormality that converges within a time constant.

(Other embodiments)
In the above embodiment, an example in which the sampling period is four times the period of the input signal has been shown. However, as described above, the minimum voltage Vmax and the minimum voltage are set as long as at least the sampling period is set longer than the period of the input signal. It is possible to accurately determine the voltage Vmin. Also, the sampling period may be a plurality of times other than four times the period of the input signal.

  In the above embodiment, a sensor circuit used for a gyro sensor has been described as an example. However, other sensor circuits may be used as long as the sensor circuit generates a sensor output by obtaining a difference between two detection signals. The present invention can also be applied to.

It is a figure which shows the circuit structure of the sensor circuit in 1st Embodiment of this invention. It is the figure which showed an example of the circuit structure of the abnormality detection circuit in the sensor circuit shown in FIG. The input signal waveform in the normal state in which no abnormality has occurred in the offset voltage is shown, (a) is a diagram showing the input signal waveform when yaw is not generated, (b) is the input when yaw is generated It is a figure which shows a signal waveform. It is a figure which shows an input signal waveform when abnormality which the offset voltage fluctuates gradually occurs. It is a figure which shows an input signal waveform when an offset voltage becomes abnormal abnormally. It is a figure which shows the circuit structure of the conventional sensor circuit. FIG. 7 shows in detail the circuit configuration of an abnormality detection circuit provided in the conventional sensor circuit shown in FIG. 6, and shows the circuit configuration of a non-inverted LPF. FIG. 7 is a diagram illustrating in detail a circuit configuration of an abnormality detection circuit provided in the conventional sensor circuit illustrated in FIG. 6, and is a diagram illustrating a circuit configuration of an inversion type LPF. It is the figure which showed the relationship of VLPF with respect to an input signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Vibrator, 20 ... Drive circuit, 30 ... Yaw detection circuit, 40 ... Abnormality detection circuit,
41 ... Peak hold circuit, 41a ... Operational amplifier, 41b ... Capacitor,
41c ... switch, 41d ... diode, 42 ... bottom hold circuit,
42a ... operational amplifier, 42b ... capacitor, 42c ... switch,
42d ... Diode, 43 ... Adder, 43a ... Operational amplifier, 43b-43d ... Resistance,
44: Window comparator.

Claims (3)

Sensing means (10) for outputting first and second detection signals corresponding to the physical quantity;
First and second voltage converting means (31, 32) for converting the voltage of the first and second detection signals;
Differential amplifying means (33) for taking a differential of the first and second detection signals voltage-converted by the first and second voltage converting means (31, 32);
Peak hold means (41) for holding the maximum voltage (Vmax) of the input signal for each predetermined sampling period using the output of the differential amplification means (33) as an input signal;
Bottom hold means (42) for holding the minimum voltage (Vmin) of the input signal for each predetermined sampling period;
Adding means (43) for outputting a voltage obtained by adding the maximum voltage (Vmax) held by the peak hold means (41) and the minimum voltage (Vmin) held by the bottom hold means (42); ,
Judgment means (43) for detecting an abnormality in the offset voltage depending on whether or not the voltage output from the adding means (43) is within a range between the upper threshold (VRH) and the lower threshold (VRL). And a sensor circuit including an offset voltage abnormality detection circuit. The sensor circuit according to claim 1, wherein the input signal is an AC signal, and the predetermined sampling period is set longer than a period of the input signal. The sensor circuit according to claim 2, wherein the predetermined sampling period is set to a multiple of the period of the input signal.

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