JPS63186165A - Defect detecting method for liquid crystal display device - Google Patents
Defect detecting method for liquid crystal display deviceInfo
- Publication number
- JPS63186165A JPS63186165A JP62019210A JP1921087A JPS63186165A JP S63186165 A JPS63186165 A JP S63186165A JP 62019210 A JP62019210 A JP 62019210A JP 1921087 A JP1921087 A JP 1921087A JP S63186165 A JPS63186165 A JP S63186165A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal lines
- selection voltage
- gate signal
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 title claims abstract description 47
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 27
- 238000000034 method Methods 0.000 title claims description 13
- 239000011159 matrix material Substances 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 8
- 239000010409 thin film Substances 0.000 abstract description 32
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 102100031048 Coiled-coil domain-containing protein 6 Human genes 0.000 description 1
- 101000777370 Homo sapiens Coiled-coil domain-containing protein 6 Proteins 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4286—Optical modules with optical power monitoring
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4287—Optical modules with tapping or launching means through the surface of the waveguide
- G02B6/4289—Optical modules with tapping or launching means through the surface of the waveguide by inducing bending, microbending or macrobending, to the light guide
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は液晶表示装置の各絵素にスイッチング素子を配
置したアクティブマトリックス型の液晶表示装置の欠陥
検出方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for detecting defects in an active matrix type liquid crystal display device in which a switching element is arranged in each picture element of the liquid crystal display device.
従来の技術
近年、液晶表示装置の絵素数増大に伴って、走査線数が
増え、従来から用いられている単純マトリックス型液晶
表示装置では、表示コントラストや応答速度が低下する
ことから、各絵素にスイッチング素子を配置したアクテ
ィブマトリックス型液晶表示装置が利用されつつある。Conventional technology In recent years, as the number of picture elements in liquid crystal display devices has increased, the number of scanning lines has increased, and in the conventional simple matrix type liquid crystal display devices, the display contrast and response speed have decreased. Active matrix liquid crystal display devices in which switching elements are arranged are increasingly being used.
しかしながら前記アクティブマトリックス型液晶表示装
置では数万個以上のスイッチング素子を広面積に配置す
るため、すべてのスイッチング素子を無欠陥に作製する
ことが困難である。そこで特開昭５９＝２４２８７６号
公報に記載されるもののようにあらかじめ、−絵素に複
数個のスイッチング素子を配置し、欠陥が発生したスイ
ッチング素子をレーザなどで絵素から切り離すことによ
り無欠陥のアクティブマトリックス型表示”ＡＭを作製
する方法がある。However, in the active matrix liquid crystal display device, tens of thousands or more switching elements are arranged over a wide area, so it is difficult to manufacture all the switching elements without defects. Therefore, as described in Japanese Patent Application Laid-open No. 59-242876, a plurality of switching elements are arranged in advance on a pixel, and the defective switching element is separated from the pixel using a laser or the like. There is a method for producing an active matrix type display (AM).
以下図面を参照しながら従来の液晶表示装置の欠陥検出
方法について説明する。たとえば前記方法として特開昭
６１−２１２８８３号公報がある。A conventional method for detecting defects in a liquid crystal display device will be described below with reference to the drawings. For example, Japanese Patent Laid-Open No. 61-212883 discloses the method.
第６図は一絵素に２個の駆動トランジスタを配置したア
クティブマトリックス型液晶表示装置の一部等価回路図
である。第６図においてｓＪ （ｊ＝ ｌ−ｎ、ただし
ｎは整数）はソース信号線。FIG. 6 is a partial equivalent circuit diagram of an active matrix liquid crystal display device in which two drive transistors are arranged in one picture element. In FIG. 6, sJ (j=l-n, where n is an integer) is a source signal line.
（１（ｉ＝ｌ〜ｍ、ただしｍは整数）、ＴＭ、。(1 (i=l~m, where m is an integer), TM,.
・ＴＳＩ Ｊ （ｔ＝Ｌ〜ｍ ｌ、ｊ＝１〜ｎ
１゜ただしｎ・ｍは整数）は薄膜トランジスタｌＰＩ
Ｊ（ｉ＝ｌ−ｍ−１，３＝１〜ｎ−１，ただしｎ−ｍは
整数）である。１は電圧印加手段である。まずゲート信
号線Ｇ３に選択電圧■。８を印加し、□ 他のゲー
ト信号線には非選択電圧Ｖ。ＦＦを印加した状態でソー
ス信号Ｓ２と８３との間の抵抗を測定する。前記選択電
圧Ｖ。Ｎとはゲート信号線に接続された薄膜１，７ジ８
．をｂ状態とさせ。・TSI J (t=L~ml, j=1~n
1゜where n・m is an integer) is the thin film transistor lPI
J (i=l−m−1, 3=1 to n−1, where nm is an integer). 1 is a voltage applying means. First, select voltage ■ is applied to gate signal line G3. 8 is applied, and □ non-selection voltage V is applied to other gate signal lines. The resistance between source signals S2 and 83 is measured with FF applied. The selection voltage V. N is the thin film 1, 7 and 8 connected to the gate signal line.
．． Let be in state b.
る電圧であり、非選択電圧Ｖ。、Ｆとはゲート信号線に
接続された薄膜トランジスタをオフ状態とさせる電圧で
ある。また選択電圧を正電圧、非選択電圧を負電圧とす
る。前記抵抗値は、選択電圧■。、により薄膜トランジ
スタＴＭＩ２とＴＳ、がオン状態となっているが、ソー
ス信号線Ｓ２とＳ３の間に接続されている他の薄膜トラ
ンジスタは非選択電圧Ｖ。ＦＦによりオフ状態になって
いるため、短絡欠陥がなければ十分に大きいはずである
。is the non-selection voltage V. , F are voltages that turn off the thin film transistor connected to the gate signal line. Further, the selection voltage is a positive voltage, and the non-selection voltage is a negative voltage. The resistance value is the selected voltage ■. , the thin film transistors TMI2 and TS are in the on state, but the other thin film transistors connected between the source signal lines S2 and S3 are at the non-selection voltage V. Since it is turned off by the FF, it should be sufficiently large if there is no short-circuit defect.
もしこの抵抗値が所定の値Ｒ０より小さいと、ソース信
号線Ｓ２と８３間に接続されている薄膜トランジスタＴ
Ｓ、とまたはＴＭアにソース・ドレイン間短絡欠陥があ
ることになる。同様にゲート信号線Ｇ４に選択電圧Ｖ。If this resistance value is smaller than a predetermined value R0, the thin film transistor T connected between the source signal line S2 and 83
This means that there is a source-drain short circuit defect in S or TM. Similarly, a selection voltage V is applied to the gate signal line G4.
Ｎを印加し、他のゲート信号線に非選択電圧Ｖ。ＦＦを
印加して、ソース信号線Ｓ２と５３間の抵抗値測定によ
り、薄膜トランジスタＴＳＴ１またはＴＭ、のソース・
ドレイン間短絡欠陥が検出できる。N is applied, and a non-selection voltage V is applied to the other gate signal lines. By applying FF and measuring the resistance value between the source signal lines S2 and 53, the source signal of the thin film transistor TST1 or TM is determined.
Drain-to-drain short circuit defects can be detected.
発明が解決しようとする問題点
しかしながら上記のような方法では、薄膜トランジスタ
のソース・ドレイン間の短絡欠陥は検出できるが薄膜ト
ランジスタのゲート・ドレイン間短絡欠陥は全く検出す
ることができなかった。また抵抗値測定のさい、正常な
薄膜トランジスタ間の所定の抵抗値は非常に大きい値と
なる。したがって抵抗値測定手段と各ソース信号線との
接続手段にリレーなどを用いると前記リレーなどの絶縁
抵抗が問題となり、測定抵抗値は不安定かつ不正確とな
る。したがって薄膜トランジスタのオン電流が微小な場
合短絡欠陥が生じているのか判定が困難となるおそれが
あるという問題点を有していた。Problems to be Solved by the Invention However, the above method can detect short-circuit defects between the source and drain of a thin film transistor, but cannot detect short-circuit defects between the gate and drain of a thin film transistor. Further, when measuring the resistance value, the predetermined resistance value between normal thin film transistors becomes a very large value. Therefore, if a relay or the like is used as a connection means between the resistance value measuring means and each source signal line, the insulation resistance of the relay or the like becomes a problem, and the measured resistance value becomes unstable and inaccurate. Therefore, when the on-current of the thin film transistor is small, there is a problem that it may be difficult to determine whether a short circuit defect has occurred.
本発明は上記問題点に鑑み、薄膜トランジスタのゲート
・ドレイン間の短絡欠陥が検出でき、かつ欠陥の検出を
確実におこなえる液晶表示装置の欠陥検出方法を１是供
するものである。In view of the above-mentioned problems, the present invention provides a defect detection method for a liquid crystal display device that can detect a short circuit defect between the gate and drain of a thin film transistor and can reliably detect the defect.
問題点を解決するための手段
上記問題点を解決するため本発明の液晶表示装置の欠陥
検出方法は任意の隣接した複数のゲート信号線に選択電
圧を印加し、かつ前記選択電圧′を印加したゲート信号
線を順次走査しながら任意のソース信号線に出力される
電流を測定することにより液晶表示装置の欠陥検出をお
こなう方法である。Means for Solving the Problems In order to solve the above problems, a method for detecting defects in a liquid crystal display device according to the present invention applies a selection voltage to a plurality of arbitrarily adjacent gate signal lines, and applies the selection voltage'. This is a method of detecting defects in a liquid crystal display device by sequentially scanning gate signal lines and measuring the current output to an arbitrary source signal line.
作用
本発明は上記した方法により以下のとおりとなる。まず
、任意の隣接した複数のゲート信号線に選択電圧を印加
し、任意のソース信号線の出力電圧を測定する。もし薄
膜トランジスタに短絡欠陥があれば前記ソース信号線に
は選択電圧の正電圧あるいは非選択電圧の負電圧があら
れれる。次に選択電圧を印加する前記ゲート信号線を１
ゲ一ト信号線ずらせて複数のゲート信号線に印加し、前
記ソース信号線の出力電圧を測定すると前回選択電圧の
正電圧があられれていた場合には非選択電圧の負電圧が
、非選択電圧の負電圧があられれていた場合には選択電
圧の正電圧があられる。以上の結果より液晶表示装置の
欠陥位置を検出することができ、る。Operation The present invention is carried out as follows by the method described above. First, a selection voltage is applied to a plurality of arbitrary adjacent gate signal lines, and the output voltage of an arbitrary source signal line is measured. If there is a short-circuit defect in the thin film transistor, a positive selection voltage or a negative non-selection voltage is applied to the source signal line. Next, the gate signal line to which the selection voltage is applied is
When applying voltage to multiple gate signal lines by shifting the gate signal lines and measuring the output voltage of the source signal line, if the positive voltage of the previous selection voltage was high, the negative voltage of the non-selection voltage will be applied to the non-selection voltage. If a negative voltage is applied, a positive selection voltage is applied. From the above results, the defect position of the liquid crystal display device can be detected.
実施例
以下本発明の一実施例の液晶表示装置の欠陥検出方法に
ついて図面を参照しながら説明する。第１図から第５図
は本発明の一実施例の欠陥検出方法を説明するためのア
クティブマトリックス型液晶表示装置の一部等価回路図
である。第１図から第５図において、２は薄膜トランジ
スタのゲート・ドレイ短絡欠陥、３は電圧計測手段、４
はピックアップ抵抗である。通常の液晶表示装置の欠陥
検出はまずゲート信号線Ｇ１とＧ２に選択電圧■。、を
印加し、任意のソース信号線に接続されたピンクアップ
抵抗５の両端の電圧を測定し、次にゲート信号線Ｇ２と
Ｇ３に選択電圧■。Ｎを印加し前記ソース信号線に接続
されたピンクアップ抵抗５の両端の電圧を測定し、次に
ゲート信号線Ｇ３とＧ、に選択電圧■。、を印加すると
いうように順に欠陥検出をおこなうが以下の本実施例で
は説明を容易にするため一絵素に着目して説明する。ま
ず薄膜トランジスタＴＳｉ（Ｊ−１）の欠陥検出方法に
ついて説明する。第１図に示すようにゲート信号Ｇ１と
Ｇ２に選択電圧Ｖ。Ｎを印加し、他のゲート信号線には
非選択電圧Ｖ。ＦＦを印加した場合を考える。この場合
トランジスタＴ Ｓ 、、 。EXAMPLE Hereinafter, a method for detecting defects in a liquid crystal display device according to an example of the present invention will be described with reference to the drawings. 1 to 5 are partial equivalent circuit diagrams of an active matrix liquid crystal display device for explaining a defect detection method according to an embodiment of the present invention. 1 to 5, 2 is a gate-drain short circuit defect of a thin film transistor, 3 is a voltage measuring means, and 4 is a gate-drain short circuit defect of a thin film transistor.
is the pickup resistance. To detect a defect in a normal liquid crystal display device, first apply a selection voltage ■ to the gate signal lines G1 and G2. , and measure the voltage across the pink-up resistor 5 connected to any source signal line, and then apply a selected voltage ■ to the gate signal lines G2 and G3. N is applied and the voltage across the pink-up resistor 5 connected to the source signal line is measured, and then a selection voltage (2) is applied to the gate signal lines G3 and G. Although defect detection is performed sequentially by applying , , and so on, in the following embodiment, in order to simplify the explanation, the explanation will be focused on one pixel. First, a method for detecting defects in the thin film transistor TSi (J-1) will be described. As shown in FIG. 1, a selection voltage V is applied to gate signals G1 and G2. N is applied, and a non-selection voltage V is applied to the other gate signal lines. Consider the case where FF is applied. In this case the transistors T S , .
ＴＭ１２およびＴＳ□がオ′ン状態となるが電流経路が
生じないためソース信号線Ｓ８に接続されたピックアッ
プ抵抗４には電圧が生じない。次に第２図に示すように
−ゲート信号線だけ選択電圧■。、を印加するゲート信
号線を移動させ、ゲート信号線Ｇ２と０３に選択電圧Ｖ
。Ｎを印加し他のゲート信号線には非選択電圧■。ＦＦ
を印加する。この場合薄膜トランジスタＴＭ、がオン状
態、第２図の点線で示すように電圧印加手段１−短絡欠
陥２−薄膜トランジスタＴＭ、−ピックアップ抵抗４に
流れる電流経路が生し、前記ピックアップ抵抗４の両端
には正電圧ｖ１が発生する。次に第３図に示すように−
ゲート信号線だけ選択電圧■。８を印加するゲート信号
線を移動させ、ゲート信号線Ｇ３とＧ４に選択電圧■。Although TM12 and TS□ are turned on, no current path is generated, so no voltage is generated in the pickup resistor 4 connected to the source signal line S8. Next, as shown in FIG. 2, only the -gate signal line is selected with voltage ■. , and apply the selection voltage V to the gate signal lines G2 and 03.
. N is applied, and non-selection voltage ■ is applied to other gate signal lines. FF
Apply. In this case, when the thin film transistor TM is in the on state, a current path flows through the voltage applying means 1 - the short circuit defect 2 - the thin film transistor TM - the pickup resistor 4 as shown by the dotted line in FIG. A positive voltage v1 is generated. Next, as shown in Figure 3-
Select voltage only for gate signal line ■. Move the gate signal line to which 8 is applied, and apply a selection voltage ■ to the gate signal lines G3 and G4.
、を印加し他のゲート信号線には非選択電圧Ｖ。ＦＦを
印加する。すると第３図の点線で示すようにピックアッ
プ抵抗４−薄膜トランジスタＴＭ、−短絡欠陥２−電圧
印加手段１に流れる電流経路が生じ、前記ピップ抵抗４
の両端には負電圧Ｖ２が発生する。, is applied to the other gate signal lines, and a non-selection voltage V is applied to the other gate signal lines. Apply FF. Then, as shown by the dotted line in FIG.
A negative voltage V2 is generated at both ends of the .
以上の結果より薄膜トランジスタＴＳ、に短絡欠陥２が
発生していることを検出できる。From the above results, it can be detected that the short circuit defect 2 has occurred in the thin film transistor TS.
薄膜トランジスタＴＳＩ（Ｊ−１）の短絡欠陥が生じて
いればゲート信号線Ｇ１ ・Ｇ、、ｌに選択電圧■。、
を印加し他のゲート信号線に非選択電圧■。ＦＦを印加
した状態でソース信号線ＳＪの出力電圧が正電圧、次に
ゲート信号線Ｇ１＋１ ・Ｇ、ヤ、に選択電圧Ｖ。Ｎを
印加し他のゲート信号線に非選択電圧■。ＦＦを印加し
た状態でソース信号線ＳＪの出力電圧が負電圧であれば
、薄膜トランジスタＴＳｉ（Ｊ−１＞に短絡欠陥が発生
していることを検出できる。If a short-circuit defect occurs in the thin film transistor TSI (J-1), a selection voltage ■ is applied to the gate signal line G1, G,, l. ,
Apply a non-selection voltage ■ to other gate signal lines. With FF applied, the output voltage of the source signal line SJ is a positive voltage, and then the selection voltage V is applied to the gate signal line G1+1. Apply N and apply non-select voltage ■ to other gate signal lines. If the output voltage of the source signal line SJ is a negative voltage with FF applied, it can be detected that a short circuit defect has occurred in the thin film transistor TSi (J-1>).
次に薄膜トランジスタＴ Ｍ １３の欠陥検出方法につ
いて説明する。第４図に示すようにゲート信号線Ｇ１と
Ｇ２に選択電圧■。Ｎを印加し他のゲート信号線には非
選択電圧■。ＦＦを印加した場合を考える。この場合薄
膜トランジスタＴＳ、がオン状態となるため、第４図の
点線で示すようにピンクアップ抵抗４−薄膜トランジス
タＴＳ、−’短絡欠陥２−電圧印加手段１に流れる電流
経路が生じ前記ピックアップ抵抗４の両端には負電圧ｖ
３が発生する。次に第５図に示すように−ゲート信号線
だけ選択電圧Ｖ。Ｎを印加するゲート信号線を移動させ
、ゲート信号線Ｇ２と０３に選択電圧■。、を印加し他
のゲート信号線には非選択電圧Ｖ。ＦＦを印加する。こ
の場合第５図点線で示すように電圧印加手段１−短絡欠
陥２−薄膜トランジスタＴＳ、−ピックアップ抵抗４に
流れる電流経路が生じ、前記ピンクアップ抵抗３の両端
には正電圧■３が発生する。以上の結果より薄膜トラン
ジスタＴＭ、に短絡欠陥２が発生していることを検出で
きる。つまり薄膜トランジスタＴＭ、、に欠陥が生じて
いればゲート信号線Ｇ１−１ ・Ｇ１に選択電圧Ｖ。Ｎ
を印加し他のゲート信号線に非選択電圧■。、Ｆを印加
した状態でソース信号線Ｓ、の出力電圧が負電圧、次に
ゲート信号線Ｇ、−Ｇ、＋、に選択電圧■。、を印加し
他のゲート信号線に非選択電圧Ｖ。Ｆ、を印加した状態
でソース信号線Ｓ、の出力電圧が正電圧となる。したが
って、薄膜トランジスタＴＭ、、に短絡欠陥が発生して
いることを検出できる。Next, a method for detecting defects in the thin film transistor T M 13 will be explained. As shown in FIG. 4, a selection voltage ■ is applied to the gate signal lines G1 and G2. N is applied, and non-selection voltage ■ is applied to other gate signal lines. Consider the case where FF is applied. In this case, since the thin film transistor TS is turned on, a current path flows from the pink-up resistor 4 to the thin film transistor TS, -' short-circuit defect 2 to the voltage applying means 1, as shown by the dotted line in FIG. Negative voltage v at both ends
3 occurs. Next, as shown in FIG. 5, the selection voltage V is applied only to the -gate signal line. Move the gate signal line to which N is applied, and apply selection voltage ■ to gate signal lines G2 and 03. , is applied to the other gate signal lines, and a non-selection voltage V is applied to the other gate signal lines. Apply FF. In this case, as shown by the dotted line in FIG. 5, a current path flows through the voltage applying means 1 - the short-circuit defect 2 - the thin film transistor TS, - the pickup resistor 4, and a positive voltage 3 is generated across the pink-up resistor 3. From the above results, it can be detected that the short circuit defect 2 has occurred in the thin film transistor TM. In other words, if a defect occurs in the thin film transistor TM, the selection voltage V is applied to the gate signal line G1-1/G1. N
Apply a non-selection voltage ■ to other gate signal lines. , F is applied, the output voltage of the source signal line S is a negative voltage, and then the gate signal line G, -G, +, is applied with a selection voltage ■. , and apply a non-selection voltage V to the other gate signal lines. When F is applied, the output voltage of the source signal line S becomes a positive voltage. Therefore, it is possible to detect that a short circuit defect has occurred in the thin film transistors TM, .
なお上述の実施例では電流検出のためピックアップ抵抗
４を各ソース信号線に接続しその両端の電圧を計測する
としたが、なにもこれに限るものではなく電流を検出で
きるものであれば何でもよい。In the above embodiment, the pickup resistor 4 was connected to each source signal line to measure the voltage across the source signal line for current detection, but the present invention is not limited to this, and any device that can detect current may be used. .
また本実施例では選択電圧を印加したゲート信号線を順
次走査するとしたが、液晶表示装置のおおよその欠陥箇
所位置がわかっている場合、その近傍に本発明の欠陥検
出方法をおこなってもその効果は変りがない。Furthermore, in this embodiment, the gate signal lines to which the selection voltage is applied are sequentially scanned, but if the approximate location of the defective location in the liquid crystal display device is known, the defect detection method of the present invention may be applied in the vicinity. There is no change.
また本発明の液晶表示装置の欠陥検出方法は、絵素コン
デンサを用いない。したがって液晶表示装置に液晶注入
前の状態であっても明らかに適用可能である。Further, the method for detecting defects in a liquid crystal display device according to the present invention does not use a pixel capacitor. Therefore, it is clearly applicable even before the liquid crystal is injected into the liquid crystal display device.
発明の効果
以上のように本発明は任意の隣接した複数のゲート信号
線に選択電圧を印加し、かつ前記選択電圧を印加したゲ
ート信号線を順次走査しながら任意のソース信号線に出
力される電流を測定するこ゛とにより、従来の方法では
不可能であった薄膜トランジスタのゲート・ドレイン間
短絡欠陥が検出でき、また抵抗値測定という手段を用い
ないため抵抗値測定手段と各ソース信号線との接続手段
の絶縁抵抗が問題となることがなく、したが、って確実
に欠陥箇所の検出をおこなえることになりその効果は大
である。Effects of the Invention As described above, the present invention applies a selection voltage to a plurality of arbitrary adjacent gate signal lines, and outputs the signal to an arbitrary source signal line while sequentially scanning the gate signal lines to which the selection voltage is applied. By measuring the current, it is possible to detect short-circuit defects between the gate and drain of thin film transistors, which was impossible with conventional methods.Also, since a resistance measurement method is not used, it is possible to detect short circuit defects between the resistance value measurement means and each source signal line. The insulation resistance of the means does not become a problem, and therefore the defect location can be reliably detected, which is highly effective.
【図面の簡単な説明】
第１図〜第５図は本発明の第１の一実施例の欠陥検出方
法を説明するためのアクティブマトリックス型液晶表示
装置の一部等価回路図、第６図は従来の欠陥検出方法を
説明するためのアクティブマトリックス型液晶表示装置
の一部等価回路図である。
Ｓ１〜Ｓｎ・・・・・・ソース信号線、０１〜Ｇｏ・・
・・・・ゲート信号線、Ｔ Ｓ 、、〜Ｔ Ｓ （ｍ−
１３（ｎ−１＋ ・Ｔ Ｍｌｌ〜ＴＭ（ｍ−１＞ （ｎ
−１＞・・・・・・薄膜トランジスタ、ＰＩＩ〜Ｐ（Ｉ
ＩＩ−１１（。−１，・・・・・・絵素コンデンサ、１
・・・・・・電圧印加手段、２・・・・・・短絡欠陥、
３・・・・・・電圧計測手段、４・・・・・・ピックア
ップ抵抗。
代理人の氏名 弁理士 中尾敏男 はか１名（４＋ＡＩ
Ｑｒ−デーＬ ！
１＋ｖｋｃ−一部た米、コソデＪブ
ＴＪｎｖｒｊＨ，ＴＭＩＩｖｎ’ｓｃ°５＜ｄ ｐ５Ｔ
）１９第 ２ 図
第 ３ ス１
ゴＳ ４ 図
第 ５ 図
第 ６ 図[Brief Description of the Drawings] Figures 1 to 5 are partial equivalent circuit diagrams of an active matrix liquid crystal display device for explaining the defect detection method of the first embodiment of the present invention, and Figure 6 is a partial equivalent circuit diagram of an active matrix liquid crystal display device. FIG. 2 is a partial equivalent circuit diagram of an active matrix liquid crystal display device for explaining a conventional defect detection method. S1~Sn... Source signal line, 01~Go...
...Gate signal line, T S , ~ T S (m-
13(n-1+ ・T Mll~TM(m-1> (n
-1>...Thin film transistor, PII~P(I
II-11 (.-1, ... picture element capacitor, 1
... Voltage application means, 2 ... Short circuit defect,
3...Voltage measuring means, 4...Pickup resistor. Name of agent: Patent attorney Toshio Nakao, 1 person (4+AI)
Qr-day L! 1+vkc-some rice, KosodeJbuTJnvrjH, TMIIvn'sc°5<d p5T
)19Figure 2Figure 3S1 GoS 4Figure 5Figure 6
Claims (2)
たアクティブマトリックス型液晶表示装置であって、任
意の隣接した複数のゲート信号線に選択電圧を印加し、
他のゲート信号線には非選択電圧を印加した状態で任意
のソース信号線の出力される電流を計測することにより
液晶表示装置の欠陥位置を検出することを特徴とする液
晶表示装置の欠陥検出方法。(1) An active matrix liquid crystal display device in which a plurality of driving transistors are fabricated in one pixel, in which a selection voltage is applied to a plurality of arbitrarily adjacent gate signal lines,
Defect detection for a liquid crystal display device, characterized in that the position of a defect in the liquid crystal display device is detected by measuring the current output from an arbitrary source signal line while applying a non-selection voltage to other gate signal lines. Method.
ことを特徴とする特許請求の範囲第（１）項記載の液晶
表示装置の欠陥検出方法。(2) A method for detecting defects in a liquid crystal display device according to claim (1), characterized in that gate signal lines to which a selection voltage is applied are sequentially scanned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62019210A JPS63186165A (en) | 1987-01-29 | 1987-01-29 | Defect detecting method for liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62019210A JPS63186165A (en) | 1987-01-29 | 1987-01-29 | Defect detecting method for liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63186165A true JPS63186165A (en) | 1988-08-01 |
Family
ID=11993005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62019210A Pending JPS63186165A (en) | 1987-01-29 | 1987-01-29 | Defect detecting method for liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63186165A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0471935A2 (en) * | 1990-08-02 | 1992-02-26 | Dambach-Werke GmbH | Circuit for supervising a matrix of bistable points |
-
1987
- 1987-01-29 JP JP62019210A patent/JPS63186165A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0471935A2 (en) * | 1990-08-02 | 1992-02-26 | Dambach-Werke GmbH | Circuit for supervising a matrix of bistable points |
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