JPS63185281A - Solid-state image pick up element - Google Patents

Abstract

PURPOSE:To reduce electrostatic capacity, and to improve random noise by providing a first group of horizontal or vertical signal lines, a second group of the signal lines divided into plural number, and the first and the second groups of switch transistors (TRs) for selection to select respectively above mentioned two signal lines groups, and subdividing the capacity CV of the verti cal signal line, and separating a part not necessary for operation. CONSTITUTION:The vertical signal lines 5-1 are lumped by every n-number of horizontal scanning lines. Incidentally, if 35 is chosen as 'n', it means that the vertical signal line is divided into seven parts approximately. When the switch TRs 6-1-6-7 for vertical signal line selection are provided respectively for the vertical signal lines 5-1-5-7, all of these drains are lumped, and it comes to be a second vertical signal line 7, and is connected to an external terminal 8. Hereby, CH does not vary similarly as before. In respect of CV, it comes to be 1/7 of the former CV because the vertical signal line is divided into seven parts. In addition to this, it comes to be the value that the diffused layer of a vertical signal line selecting switch is added. Accordingly, the random noise of a MOS type image pick up element can be reduced, and a high sensitivity camera can be constituted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state image sensor, and particularly to an MO8 type image sensor that sequentially scans and reads out photoelectric conversion elements arranged in a two-dimensional manner using an X and Y switch matrix. This is related.

[Conventional technology]

A solid-state image sensor consists of two-dimensionally arranged photoelectric conversion elements.
It sequentially scans in synchronization with the scanning cycle of the television, and extracts the signal charges accumulated in the photoelectric conversion element in time series. Solid-state image sensing devices can be roughly divided into two types: a MOS type that reads out signals via an XY switch matrix, and a charge transfer type that uses a COD or the like that has a self-scanning function. FIG. 2 shows a configuration example of a MOS type which is an X-Y address scanning type. The structure of Figure 2 is published in Japanese Patent Application Laid-Open No. 59-144278.
It is detailed in the publication and the Television Society Technical Data (TV Society Technical Report ED891, September 27, 1985).

In the MO8 type solid-state image sensor shown in Fig. 2, - vertically for each pixel,
MO8I-ransistor switch 21.22 for horizontal selection
is provided. The signal of each pixel is the vertical scanning pulse line 2
3 and the horizontal scanning pulse line 24 by opening and closing the MOS transistor switches 21 and 22, respectively. 25 in Figure 2
is a horizontal shift register that generates horizontal scanning pulses, 26
is a vertical shift register that generates vertical scanning pulses. A start pulse and two-phase clock pulses are required to operate each shift register 25, 26, but are omitted from FIG.

Horizontal and vertical MOS transistor switch 2]-22
The signal charges selected and read out through the pixel 2 are sent to a horizontal signal line 27 that is common to all pixels in the horizontal direction.

At the end of each horizontal signal line 27 is a horizontal scanning line selection MO8 which is opened and closed by the vertical scanning pulse 23 that selects each scanning line.
An I-transistor switch 28 is arranged. The drain of a MOS transistor switch 28 disposed at the end of each horizontal signal line 23 is connected to a vertical signal line 29.

The output of the vertical signal line 29 is drawn out to the outside of the image sensor and connected to a preamplifier 30.

One of the features of the MO3 type image sensor is that it can easily be made into multi-line output. In FIG. 2, the structure is such that two rows of horizontal signal lines 27 and 31 are read out simultaneously. That is, the same vertical scanning pulse output is applied to the two horizontal scanning lines 23.degree. 32. The interlace operation at this time is performed by an interlace changeover switch 33 provided every two horizontal scanning lines. That is, if the interlace switch 33 is switched for each field between the direction of the solid line arrow and the direction of the dotted line arrow, the center of gravity of the video signal moves to the interlacing position, so that interlacing can be realized.

The features of the device having the structure shown in FIG. 2 can be summarized as follows.

1) Since multi-wire output lines can be easily realized, when configuring a single-chip color camera using a mosaic color filter, a configuration with less color moire is possible.

ii) Very little vertical smear phenomenon occurs in solid-state imaging devices. Compared to the conventional structure, the time for accumulating vertical smear charges is much shorter, and at the same time, although not described in detail, the reset MO8I-transistor 34 installed for each horizontal signal line (24°31) in FIG. By resetting the horizontal signal line 27 to a constant potential every horizontal blanking period, the smear is further reduced, and 100 dB or more is possible.

)1]) Can be manufactured using conventional MO8TCO8
Cost can be reduced.

As described above, the MO3 type image sensor having the structure shown in FIG. 2 has many features and is an excellent image sensor.

[Problem that the invention seeks to solve]

Even though the MO8 type image sensor has many features as described above, one item that still needs to be improved is the improvement of random noise.

FIG. 3 shows an equivalent circuit of random noise of the MO8 type image sensor having the structure shown in FIG. The details of the random noise are described in the materials of the Electronic Devices Research Group of the Television Society of Japan, so this specification will limit itself to the results and qualitative explanation.

First, FIG. 3 will be explained. Cpn is the capacitance of the photodiode, that is, the signal storage capacitance. RXY is X.

This value is the sum of the ON resistance of the Y selection transistor. CH and RH are the capacitance of the horizontal signal line 23 and the resistance of the horizontal signal line 23. Rs is the N resistance of the horizontal scanning line selection switch transistor 28. Furthermore, Rv and Cv indicate the resistance and capacitance of the vertical signal line 29, and since it is appropriate to consider the vertical signal line 29 as a distributed constant circuit of CR, the equivalent circuit can be written in the form shown in Figure 3. .

CL is the capacitance at the output terminal of the element and is mainly determined by the capacitance of the bonding pad, the capacitance of the package, etc.

C1 is the input capacitance of the preamplifier, and en is the noise generated from the equivalent noise resistance (Req) of the first stage amplification element of the preamplifier expressed in voltage. R5 is a signal load resistance value.

The noise of the MO8 type image sensor is expressed as the following current values Int to Ins at each stage shown in FIG.

Inz”=4KT”Cpn-fcp-B −
a)...(3) ■n52=4KT・-π"(Cu+Cv+Cb+C1)
2R(1qB 8...(4) where K: Boltzmann's constant, T: absolute temperature, fcp: horizontal clock frequency, and B: video signal band.

Int in equation (1) has a form that is not related to Rxv, but like reset noise, this is the so-called KT
This is because it behaves the same as C noise.

In equation (2), the coefficient of RH is 1/3, and in equation (3), the coefficient of RH should be (Co+Cv)'', but it is (C
H2+CHCv+-CV'') because the horizontal signal line 23 and vertical signal line 29 are represented as distributed constant circuits, and the amount of noise is alleviated.

Next, try calculating the noise by giving real numbers to these equations (1) to (4). An example of each parameter value is shown below.

Cpn: 0.02pF, fcp: 5MHzB
: 3MHz CH: 2pFR)I:3
00 Ω Rs: 1 to ΩRv near 0Ω
Cv: 8pF CL: 1pF Ct: 9pFReq
Near 0Ω R1: 2MΩ Using the above values ■. Calculating engineering ~ In4, engineering, 1 = 77 p Ar
m5 I nz + I ns = 1601) Arm5I R
4: 1 3 0 p Arm5Ins=425
p Arm+Ins= 160 p Arm5 The total is 505 pA□9.

When the noise power ratio of each term of the MO8 type image sensor is expressed as a percentage in FIG. 4, it can be seen that the main noise is InB preamplifier noise. It goes without saying that reducing the Req of the first-stage amplification element is effective in improving preamplifier noise, but it is especially effective to reduce the preamplifier noise by reducing the capacitance (CH + Cv
x, 0C1) is very effective. Also, decreasing Co and Cv is I ++41 I
This is particularly effective since it is also related to nB.

In order to reduce random noise, which is a problem with the MO8 type image sensor, each noise source (RH, Rv) is used.

Although it is a matter of course to improve the capacitance (ReqtRf, etc.), it can be understood that reducing each capacitance is very effective.

[Means for solving problems]

As mentioned above, reducing the capacitance is effective in improving the random noise of the MO8 type image sensor. Of the current constants, C8, which is determined by external elements, can be optimally designed to match (CH+CV+CL=Ct) with the equivalent output capacitance of the element (CH+Cv+Ct,), leaving plenty of room for future improvement. ing.

The problem is that it is easy to imagine that if the capacitance inside the element, especially Cv, which has a large value, can be reduced, a large effect of noise improvement can be obtained.

Therefore, the gist of the present invention is to subdivide the capacitance Cv of the vertical signal line and cut off portions unnecessary for operation, thereby reducing capacitance and improving random noise.

[Effect]

The main component of the capacitance of the vertical signal line is the capacitance of the drain diffusion layer of the horizontal scanning line selection switch 28. Since the vertical signal line 29 has the role of receiving signal charges from each horizontal signal line 23 via the selection switch, the diffusion layer of the MOS transistors for one field of scanning lines (approximately 250 lines) is Since the wiring capacitance and wiring capacitance are all added up, the capacitance becomes large.

Originally, from each horizontal signal line, only the capacitance of the selected signal line is used, without adding unnecessary capacitance of other signal lines.
It is easy to imagine that the lowest noise will be achieved if the signal is guided directly to the preamplifier. However, this requires a large number of output leads and preamplifiers unless a preamplifier is connected to each horizontal signal line, which is difficult to implement in terms of power consumption.

Therefore, in the present invention, the horizontal signal lines are not combined into one vertical signal line as in the prior art, but are divided into a plurality of lines in the vertical direction. For example, if it is divided into 1o, it means that 250 signal lines in one field are grouped into 25 lines each. In order to take out the combined outputs of 25 lines to the outside, a new selection transistor switch is installed for each output line (25 lines), and the drains of these 10 sets of transistor switches are combined into one and sent to the outside. Configure to pull out. With this configuration, the capacity for the other nine unnecessary sets can be cut off.

With this circuit configuration, the number of selection transistors has increased, which means that a new noise source has been added, but as mentioned above, capacitance has a greater effect on noise than the resistance stand, so overall This will result in lower noise.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
In the figure, 1 is a horizontal shift register, and 2 is a vertical shift register. In FIG. 1, the interlace circuit is also included in the vertical shift register 2, so the interlace circuit is not particularly shown in the figure. The structure of each horizontal line (the structure up to the horizontal scanning line selection switch 3) is the same as that of the conventional example shown in FIG. 2, so the explanation will be omitted. Figure 1 shows the reset transistor (
34) in FIG. 2 is also omitted because it is not particularly relevant to the present invention.

That is, the portion surrounded by a dashed line 4 in FIG. 1 is the same as the conventional one. Figure 1 shows the conventional element structure (second
In contrast to the example shown in Figure) which has a multiple output line configuration, this is shown as an example of a negative line output configuration. Even with a multiple readout line structure, the gist of the present invention is not impaired.

The most important point of the present invention is that the horizontal scanning line selection switch 3
The following is the configuration. As shown in FIG. 1, unlike the conventional configuration, the vertical signal lines 5-1 are grouped into every zero horizontal scanning line. By the way, if n is chosen to be 35 lines, the vertical signal lines are divided into approximately 7 parts (1 field has 250 horizontal signal lines). These vertical signal lines 5-1 to 5- divided into seven
7 are provided with vertical signal line selection switches 1 to transistor rows 1 to 6-7, respectively. The drains of the vertical signal line selection switch transistors 6-1 to 6-7 are all combined to form a second vertical signal line 7 and connected to an external terminal 8. A pulse is applied to the gates 9-1 to 9-7 of the vertical signal line selection switch transistors so that the switch transistors are turned on while the scanning line connected to each switch transistor is selected. The pulse timing at this time is shown in FIG.

FIG. 5(a) is a waveform schematically representing a video output signal for one field. FIG. 5(b) shows the waveforms applied to the gates I of the vertical signal line selection switch transistors 9-1 to 9-7. The vertical signal line selection switches 6-1 to 6-7 are sequentially switched in the horizontal blanking period every nH. The waveform of FIG. 5(b) can be obtained as the output of a shift register with nH as the tarock.

Although this shift register is not shown in Figure 1,
There is no need to explain that it can be formed on the image sensor in the same way as other shift registers.

FIG. 6 shows an equivalent circuit of FIG. 1. In addition to the conventional equivalent circuit shown in Fig. 3, vertical signal line selection switches 6-1 to 6-7
and the second vertical signal line 7 is added.

■ Among the noises from I nl' to I nil' in FIG. E' to I n4' are the same as the conventional formula. In addition, Inll' is the load resistance noise of the preamplifier, and has the same formula as Ins in the conventional formula. A new noise component I caused by adding the vertical signal line selection switches 6-1 to 6-7 and the second vertical signal line 7 below.
n6' + Ink' + and I n7', which is the noise of the first stage TR of the preamplifier, which is different from the conventional formula, will be described.

I n5' to I ++7' is In6'''=4. KT-π2(CH+CV)2RO
B”-(6)+CVCO)RV2
-(7)In7' 2=4KT
-πxccH+cv+co+cL+cs)2Req
−(8).

Here, Ro is the vertical signal line selection switch 6-1 to 6-7.
, RV2 is the resistance value of the second vertical signal line,
Co is the capacitance of the second vertical signal line.

An example of the effect of this embodiment (in the case of n=7) will be estimated.

As mentioned before, engineering. 1' to I n8' are the conventional noise Inz to I n8'. The same applies to +, expressions, and constants.

In the formula of I n4', which is the gist of the present invention, CH is unchanged from the conventional formula. Considering Cv, the vertical signal line is 7
Since it is divided, the conventional Cv (8pF) is 1. /'7 1
．． It becomes 1 pF. In addition to this, the value is the addition of the diffusion layer of the vertical signal line selection switch. If the ON resistance Ro of the vertical signal line selection switch is now set to 200Ω, the capacitance of the diffusion layer will be the same as that of the conventional horizontal scanning line selection switch (ON
It is considered to be about 5 times the resistance (1Ω to 1Ω), so the capacitance of the vertical signal line is 8pF minus 2.5p for the Afl wiring, and the value obtained by subtracting F is 5.5 p F divided by the number of scanning lines (250) is 5 5.5÷250X5=0.11pF.

Therefore, Cv is 1.1+0.11=1.21pF.

■. Go in 6' is the capacitance of the second vertical signal line, and this is the capacitance of the vertical signal line selection switch TR (6-1 to 6-7) 7.
It is determined by the individual diffusion layers and the AII wiring that brings them together.

If the resistance value of the An wiring is now set to 20Ω, the capacitance of the AQ wiring is approximately 1.5 pF.

Therefore, Co is 0.11×7+1.5×2.3pF.

For CL HCI, Req has the same value as before. When calculating using this constant, I na' 20 p Arm5 Ins' = 110 p Ar+nsI nB' =
52 p Arm5 I n7' = 3 1 3 p Arm5,
Total noise level■. ' is In''=412nArms.

In other words, it can be seen that the noise is improved by about 1.8 dB compared to the conventional noise.

This trial calculation is just an example, and there is no need to explain that the effects of this embodiment vary depending on the number of divisions and the design of the vertical signal line selection switch.

Next, a method of generating switching pulses to be supplied to the vertical signal line selection switch in the configuration of this embodiment will be described. In the above example, it was described that it can be realized with a configuration similar to that of a vertical scanning shift transistor (that is, a shift register for each period of an nH scanning line). Here, another embodiment in which a gate circuit is provided will be described.

An example of this is shown in FIG. In this embodiment, one division out of n divisions is shown. That is, if all the outputs 10-1 to 10-n of the vertical shift registers applied to the gates of the horizontal scanning line selection switches 3-1 to 3-n are drawn out and applied to the OR gate circuit 11, one division is achieved. While the scanning line in the middle is selected, OR gate circuit 1
1 output can always be in the ON state. The output 12 of the OR gate circuit 11 is connected to the vertical signal line selection switch T.
By adding it to the gate of R9, it becomes possible to automatically select a vertical signal line.

〔Effect of the invention〕

As described above, by using the present invention, random noise of MO8O8 type elements can be reduced, and a highly sensitive camera can be constructed.

It goes without saying that the present invention is applicable not only to a horizontal readout type MO8 type image pickup device but also to a normal so-called MO8O8 type device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a device configuration showing an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a conventional horizontal readout MO8O8 type device, FIG. 3 is a diagram showing an equivalent circuit of FIG. 4 is a diagram showing the random noise power ratio of each part of the conventional element, FIG. 5 is a timing chart diagram explaining the present invention in detail, FIG. 6 is a diagram showing an equivalent circuit in the configuration of FIG. 1, and FIG. FIG. 7 is a diagram showing another embodiment of the selection pulse generation method of the present invention. DESCRIPTION OF SYMBOLS 1...Horizontal shift I-register, 2...Vertical shift register and interlace circuit, 3...Switch transistor for horizontal signal line selection, 5...Vertical signal line, 6-1
~6-7... Vertical signal line selection switch transistor when divided into seven, 7... Second vertical signal line. Agent Patent Attorney Masaru Koyo5.夛-). :, , 1 ＼ d 82 mouth x5 纺 3 concave 4 fig'IIL+ product 5 圀￥-J 6 concave 7 concave-n

Claims (1)

[Scope of Claims] 1. In a solid-state imaging device comprising a photoelectric conversion element and a switch array for selecting the same, and having horizontal and vertical scanning circuits for sequentially reading out the photoelectric conversion element, when reading out the output of the photoelectric conversion element, A horizontal or vertical first signal line group used in common, a first selection switch transistor group for selecting the first signal line group, and a first selection switch transistor group coupled via the first selection switch transistor group. A solid-state imaging device comprising: a second signal line group divided into a plurality of vertical or horizontal lines; and a second selection switch transistor group for selecting the second vertical or horizontal signal line group divided into a plurality of lines. 2. In the solid-state imaging device according to claim 1, a second selection switch transistor group for selecting the second vertical or horizontal signal line group divided into multiple groups is provided separately from the vertical and horizontal scanning shift registers. A solid-state imaging device characterized in that it is sequentially opened and closed by a shift register. 3. In the solid-state imaging device according to claim 1, a second group of vertical or horizontal signal lines divided into a plurality of first parts is selected.
A solid-state imaging device characterized in that a group of selection switch transistors is driven with an OR output of a plurality of pulses that drive a first selection switch transistor included in one block divided into a plurality of blocks.