JPS63184499U - - Google Patents
Info
- Publication number
- JPS63184499U JPS63184499U JP1987074660U JP7466087U JPS63184499U JP S63184499 U JPS63184499 U JP S63184499U JP 1987074660 U JP1987074660 U JP 1987074660U JP 7466087 U JP7466087 U JP 7466087U JP S63184499 U JPS63184499 U JP S63184499U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- write
- eeprom
- processor
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims description 2
- 230000010365 information processing Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Description
第１図は、この考案を適用した一実施例のＥＥ
ＰＲＯＭ書込み防止回路を中心としたブロツク図
である。
１……マイクロプロセツサ、２……ＥＥＰＲＯ
Ｍ、３……書込み制御回路、４……データバス、
５……アドレスバス及び制御バス、６……ライト
イネーブル信号出力線、７……スイツチ。
Figure 1 shows an EE of an embodiment to which this invention is applied.
FIG. 2 is a block diagram centered on a PROM write prevention circuit. 1...Microprocessor, 2...EEPRO
M, 3...Write control circuit, 4...Data bus,
5...Address bus and control bus, 6...Write enable signal output line, 7...Switch.
Claims (1)
続されたＥＥＰＲＯＭと、前記プロセツサの制御
バスに接続され、前記ＥＥＰＲＯＭをライトイネ
ーブル状態にする信号を出力する書込み制御回路
を備える情報処理装置において、前記ＥＥＰＲＯ
Ｍのライトイネーブル端子と前記書込み制御回路
の前記信号の出力端子との間に前記信号が前記Ｅ
ＥＰＲＯＭに入力することを阻止する信号遮断回
路を挿入したことを特徴とするＥＥＰＲＯＭ書込
み防止回路。 An information processing device comprising: an EEPROM connected to an address bus and a data bus of a processor; and a write control circuit connected to a control bus of the processor and outputting a signal for setting the EEPROM in a write enable state.
The signal is connected between the write enable terminal of E and the output terminal of the signal of the write control circuit.
An EEPROM write prevention circuit characterized in that a signal cutoff circuit is inserted to prevent input to an EPROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987074660U JPS63184499U (en) | 1987-05-19 | 1987-05-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987074660U JPS63184499U (en) | 1987-05-19 | 1987-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63184499U true JPS63184499U (en) | 1988-11-28 |
Family
ID=30920079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987074660U Pending JPS63184499U (en) | 1987-05-19 | 1987-05-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63184499U (en) |
-
1987
- 1987-05-19 JP JP1987074660U patent/JPS63184499U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63184499U (en) | ||
| JPS62169831U (en) | ||
| JPH0317834U (en) | ||
| JPS6266329U (en) | ||
| JPS59151331U (en) | Microprocessor control circuit | |
| JPH0179164U (en) | ||
| JPH01153753U (en) | ||
| JPH0277747U (en) | ||
| JPH01165659U (en) | ||
| JPS6184953U (en) | ||
| JPS62169850U (en) | ||
| JPS62175336U (en) | ||
| JPS60123003U (en) | numerical control device | |
| JPS63118601U (en) | ||
| JPS5810092U (en) | Alarm circuit with clock day designation function | |
| JPS6077149U (en) | signal transmission system | |
| JPS5828938U (en) | Anti-chattering device | |
| JPS60132699U (en) | integrated circuit | |
| JPH02113899U (en) | ||
| JPS5890449U (en) | verification card | |
| JPS5996611U (en) | Direct memory access method | |
| JPS6377282U (en) | ||
| JPS60123002U (en) | Function selection circuit | |
| JPS6022056U (en) | Border device | |
| JPS63139647U (en) |