JPS63181983U

JPS63181983U -

Info

Publication number: JPS63181983U
Application number: JP7273687U
Authority: JP
Priority date: 1987-05-15
Filing date: 1987-05-15
Publication date: 1988-11-24

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の各ブロツクの出力信号を示す線
図、第３図は従来例を示すブロツク図、第４図は
第３図の動作説明図である。１……トリガ信号受信再生手段、２……パター
ン記憶手段、３……パターン判定手段、４……信
号補正手段。 FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a diagram showing output signals of each block in FIG. 1, FIG. 3 is a block diagram showing a conventional example, and FIG. 4 is an explanatory diagram of the operation of FIG. 3. 1...Trigger signal reception and reproduction means, 2...Pattern storage means, 3...Pattern determination means, 4...Signal correction means.

Claims

[Claims for Utility Model Registration] A trigger demodulation circuit comprising a trigger signal receiving and reproducing means and a signal correcting means for correcting the output of the trigger signal receiving and reproducing means and outputting it as a predetermined trigger signal, comprising: Between the reproduction means and the signal correction means, a pattern storage means for storing the output of the trigger signal reception and reproduction means, and a pattern storage means for storing the output of the trigger signal reception and reproduction means, and a pattern storage means for determining whether the trigger signal stored in the pattern storage means is a signal related to a repeating pattern specified in advance. What is claimed is: 1. A trigger demodulation circuit comprising: pattern determination means for determining whether a trigger signal is generated and outputting a matching signal for forming a trigger signal.