JPS63181380A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the space of a tunnel current region sufficiently for assuring high integration by a method wherein a protrudent piece is formed on at least one of respective electrodes to form an overlapping part thereof. CONSTITUTION:A discharging electrode 16 and a feeding electrode 18 holding a floating gate electrode 17 are formed in lamination. At this time, a protrudent piece 171 is formed on at least one of respective electrodes 17 forming an overlapping part thereof to set up a tunnel current region. Thus, the space of tunnel current region can be reduced sufficiently. Through these procedures, when any data are written in or erased, the capacity coupling ratio between a gate electrode and a drain electrode to control the potential of floating gate electrode 17 can be increased sufficiently without specifying a large space of capacity coupling part so that the space of storage elep may be reduced sufficiently enabling a storage device to be highly integrated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a non-volatile non-volatile device in which electrical information can be written and stored information can be retained without applying external staining force. The present invention relates to a semiconductor memory device.

[Prior Art] A semiconductor memory device as described above is known as, for example, an EEPROM. Figure 9 shows the conventionally known EE
This figure shows the structure of one memory element portion of a PROM, in which a source electrode region I2 and a drain electrode region 13 are formed in a semiconductor substrate Z1, and a drain region 14 is formed in a manner continuous with the drain electrode region 13. is starting to form. An r-) insulating film 15 is formed on the surface of such a semiconductor substrate, and a discharge electrode 16 is formed on this r-) insulating film 15. A floating ff-4 electrode 17 is formed so as to partially overlap the discharge electrode I6. In this case, this floating gate electrode 1
Reference numeral 7 is set to partially overlap the drain region 14, and an injection electrode 18 is further formed on the floating gate electrode I7 with an insulating layer interposed therebetween.

That is, it has a structure in which three layers are stacked on the semiconductor substrate 11 K, the exhaust electrode 16, the floating r-) electrode 17, and the injection electrode 18, and the floating f-) electrode I7 and the drain region 14. The area shown by the diagonal lines in the figure where the two overlap with each other is set as the tunnel area. And injection electrode 18
Control r-) voltage signals Vgl and Vg2 are supplied to the and drain electrodes 16, respectively, and a drain voltage Vd is applied to the drain electrode region 13, and the floating gate electrode 17 The potential of this electrode and the drain region 1 indicated by diagonal lines in the diagram is
It is mainly controlled by the capacitive coupling part 19 with 4.

In this case, the above-mentioned capacitive coupling portion 19
The area of the tunnel current region is determined by the area of the tunnel current region, and the area of the device is restricted by the area of the tunnel current region. In other words, when the area of the tunnel current region is large, the element area cannot be made sufficiently small, making it difficult to achieve high integration, and at the same time, it is disadvantageous in terms of electron retention characteristics. Become.

[Problems to be Solved by the Invention] This invention was devised in view of the above-mentioned points. In particular, the area of the tunnel current region can be made sufficiently small, and the purpose of high integration can be effectively achieved. It is an object of the present invention to provide a nonvolatile semiconductor memory device that enables

[Means for Solving the Problems] That is, the nonvolatile semiconductor memory device according to the present invention is configured such that the discharge electrode and the injection electrode are stacked with the floating gate electrode in between. In this case, a protruding piece is formed on at least one of the above-mentioned electrodes, and this protruding piece forms an overlapping part of each of the above-mentioned electrodes, so that a tunnel current region is set. It is something that can be done.

[Function] The nonvolatile semiconductor memory device as described above can be constructed in a state where the area of the tunnel current region is sufficiently small. Therefore, when writing and erasing information, the capacitive coupling ratio at the capacitive coupling part between the r-to electrode and the drain region, which controls the potential of the floating gate electrode, is determined by the area of the capacitive coupling part. can be made sufficiently large without having to be set particularly large, and the area of the memory element can be made sufficiently small. Therefore, high integration becomes possible, and at the same time, information electron retention characteristics are improved.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows one memory element part of a nonvolatile semiconductor memory device, in which a semiconductor substrate 11 made of p- type silicon has an N+ source electrode part 12 and a drain electrode part 13 formed thereon. , this drain electrode part 13
An N- type drain region I4 is formed in a continuous state.

On the surface of such a semiconductor substrate 11, silicon oxide (
An f-) oxide film I5 made of S102) is formed, and a discharge electrode 16 made of polysilicon is formed on this r-) oxide film I5.

A floating gate electrode 17 made of polysilicon is further formed on the e-) oxide film 15 so as to partially overlap with the drain region. Here, in this floating f-) electrode 17,
A strip-shaped projecting piece 171 is integrally formed from the negative side toward the discharge electrode 16, and this projecting piece 171 is arranged so as to overlap the discharge electrode I6 with the insulating layer 151 in between. It is set. Then, further insulating layer 1
52, the discharge electrode I6 and the injection electrode 18 overlap at the piece xix where the injection electrode 18 made of polysilicon is formed on the discharge electrode 16 and on the protruding piece 171 of the floating gate electrode 17. A tunnel current is passed through this overlapped area to cause electrons to flow. In this case, the injection electrode 18 and the protruding piece 17 of the floating gate electrode I7
A large number of small irregularities are formed on the lower surface of each of the electrodes 1, and electric field concentration in these irregularities is utilized to cause a tunnel current to flow through an insulating layer made of a relatively thick oxide film.

The injection electrode 18 is supplied with a control voltage v1, and the discharge electrode 16 is supplied with a control voltage v2. This is performed through the capacitive coupling portion 19 with the region 14, and is mainly determined by the drain voltage V.

In the memory element configured in this way, the protruding piece 17
Fowler-Nordheim (Fowler-Nordheim) in the insulating layers 151 and 152 due to electric field concentration on the unevenness of the lower surface of the injection electrode I8 and the injection electrode I8, respectively.
Through tunneling, injection (writing) of electrons from the injection electrode I8 to the electrode I7 (70-tingff-) and ejection (erasing) of electrons from the floating r-) electrode 17 to the ejection electrode 16 are performed. Become.

That is, in this memory element, the floating r
-) Depending on whether electrons are accumulated in the electron NI7 or not,
MOS) Rannosta (Territory H12, Z s.

20, the threshold voltage V of the electrode 16, etc.);
will be shifted, and will be given a memory function.

When writing or erasing information in such a memory element, as described above, 70-
The potential of the ting gate electrode 17 is mainly controlled by capacitive coupling between the electrode 17 and the drain region 14. FIG. 2 shows a simple equivalent circuit of the capacitance associated with this floating r-) electrode 17.

In this equivalent circuit, C1 is a floating f-)
Capacitance between electrode 17 and drain region 14, Ctu
nv is the capacitance between the injection electrode 18 and the floating gate electrode 17, C is the capacitance between the floating gate electrode I7 and the drain electrode 16, and CgOX is the capacitance between the floating gate electrode I7 and the substrate 1
It is the capacitance between 1 and 1.

That is, during write operation, the drain voltage V
, to a positive (+) potential, the potential V- of the injection electrode 18 and the substrate 11 to the ground potential, and the potential Vg2 of the discharge electrode 16.
is a floating e-) positive potential (hal
(referred to as f+). Further, during erasing, the potential v2 of the discharge electrode 16 is set to a positive (+) potential, the drain potential V and the substrate II are set to the ground potential, and the potential of the injection electrode 18 is set to the potential V 1 f half .

When a memory cell array as shown in FIG. 3 is made using the above-mentioned memory elements, the potential relationship of each electrode part when writing is performed on the memory element shown by ■ is shown in the figure below. It is something that exists.

In addition, the diagram (B) shows the potential relationship of each electrode when erasing the memory element also indicated by ■. The potential relationship shown in FIG. 3 is only one example, and other potential relationships are also possible.

In the equivalent circuit shown in FIG. 2, the shift amount of the threshold voltage of the storage element can be estimated by the following equation.

Note that the equation (1) is for writing, and the equation (2) is for erasing.

(2) However, here, IVtunl is the minimum voltage applied to the tunnel oxide film necessary to cause tunneling, and this voltage 1vtunl is estimated by the following formula.

However, ttun: thickness of tunnel oxide film, m: electrode 17
．． Electric field intensification coefficient due to single field concentration in the uneven portion of 171,] Utun: Minimum electric field required for Fowler-Nordheim tunneling.

The results of calculations based on various setting conditions using equations (1) to (3) shown above are shown in FIGS. 4 and 5. Here, Etun = I x 10 V / crtt (+) potential = 20 V, half = 10 V gate oxide film 1
In this case, the actual value of m is 2.
It is considered to be ~5.

This calculation is first performed for the memory element according to the embodiment shown in FIG. 1, and is shown in FIG. Also the 9th
The conventional example shown in the figure was also calculated under the same conditions, and this is shown in FIG. 5 in correspondence with FIG. 4.

Here, by using the above calculation example and comparing the values of Sp when V is 5V, the superiority of the memory element shown in the example will be explained as follows.

First, in FIGS. 4 and 5, (A) is r ttu
This is the case where n = 730XJ, and since the film thickness is large in this case, the effect of providing the protruding piece 171 on the floating gate electrode 17 and thereby setting the tunnel current region is not very large. However, a reduction effect of 1 μm in the length D of the coupling portion 19 was obtained. Furthermore, if the ttun is set thin like r400XJ and r300XJ, it will be 3.72μ as above.
A reduction effect of ms5.25μm is expected,
It is possible to reduce the memory element size.

As is clear from the above, by reducing the area of the tunnel portion, S2. This makes it possible to reduce the overall device size. Furthermore, by reducing the area of the tunnel portion, it is expected that the charge retention characteristics will be improved.

Here, for reference, the manufacturing process of the memory element will be briefly described as described above.

First, a source electrode region I2 and a drain electrode region 13 are formed using an N+ region in a P- type silicon substrate 11, and an N- type drain region 14 is further formed. Then, an r-) oxide film 15 is formed on the surface of the substrate 11 in these regions by thermal oxidation, and an exhaust electrode I6 is formed of polysilicon. At this time, the polysilicon film is appropriately doped with phosphorus as an impurity, and in this state, the surface of the formed polysilicon film is uneven. Then, when this is thermally oxidized, an insulating layer 1 of the oxide film is formed on the surface of the polysilicon film (exhaust electrode).
51 is formed, and the above-mentioned irregularities are inherited on the surface. However, the irregularities on the surface of the polysilicon are recrystallized by heat treatment, and the crystal grains become larger, resulting in a smoothed state.

In this state, a 70-ring gate electrode 11 made of 1β silicon is laminated so as to partially overlap the discharge electrode 16, and the unevenness inherited on the surface of the insulating layer 151 forms an r-) electrode. 17, that is, the lower surface of the protrusion piece 171 portion. In this state, unevenness exists on the surface of the polysilicon film constituting the r-to electrode I7. Then, in this state, the surface of the gate electrode 17 is further thermally oxidized to form an insulating layer 152 made of an oxide film, and the surface of this insulating layer 1520 inherits unevenness in the same manner as described above, and a polygonal layer is formed on the surface of the insulating layer 1520. An extraction electrode 18 made of silicon is formed.

FIG. 6 shows another embodiment, in which instead of forming a protrusion W piece 171 on the floating r-) electrode 17 as in the previous embodiment, protrusion pieces 181 are formed on the injection electrode 18 and the discharge electrode I6, respectively. and 161, and the protruding pieces 181 and 161 form the 70-inch r-1 electrode 17.
are superimposed on each other to form a tunnel current region.

With this configuration, as can be understood from the cross-sectional structure in Figure a3), the three-layer electrode structure can be configured in two stages, which is advantageous in terms of the back fabrication of the device. Furthermore, it is also possible to arbitrarily change the positions of the protruding pieces 161 and 181 to create a three-tiered structure.

FIG. 7 shows yet another embodiment, in which the injection electrodes 18 are set at greatly different positions,
One corner of this electrode 18 is curved so that it overlaps with the floating gate electrode 17. Further, in the embodiment shown in FIG.

A protruding piece 182 is formed on the independently set injection electrode 18, and the protruding piece 1112 overlaps the 70-inch r-t electrode 18.

[Effects of the Invention] As described above, in the nonvolatile semiconductor memory device according to the present invention, the area of the tunnel current region due to the overlap between the 70-chiing r-) electric current, the injection electrode, and the discharge electrode is effective. Therefore, the area of the region for capacitive coupling with the drain region of the floating r-) electrode can be set small. Therefore, it is possible to reliably reduce the area required for a memory element, which is highly effective for achieving high integration, and at the same time, the electron retention characteristics are improved, making it reliable as a non-volatile memory device. Sexuality will also be improved.

[Brief explanation of the drawing]

FIG. 1 shows a memory element according to an embodiment of the present invention, in which E9 is a plan view, E9 is a cross-sectional view taken along line bb in FIG. 2, and FIG. FIG. 3 is a simplified equivalent circuit diagram of the capacitance of the above element; FIG.
5 and 5 are diagrams illustrating a comparison of characteristic calculation examples of the memory element of the above embodiment and a conventional memory element, and FIGS.
Figures 9 and 9 are diagrams explaining other embodiments of the present invention, respectively.
Figure (A) is a diagram showing a planar configuration of a conventional memory element, and ω) in the same figure is a bb@ cross-sectional configuration diagram of Figure 2. 11... Semiconductor substrate, 12... Source electrode region, 1
3... Drain electrode region, 14... Drain region,
15...r-) Oxide film, I6... Exhaust electrode, 17.
...Floating gate electrode, 18...Injection electrode,
16Z. 171.181,182...Protruding piece. Applicant's representative Patent attorney Takehiko Suzue (A>'; 23rd prisoner, 4th CI!J 5th prisoner, Figure 6, Figure 8)

Claims (1)

[Scope of Claims] An exhaust electrode and an injection electrode formed on a semiconductor substrate with a gate oxide film interposed therebetween, and further layered on a drain region of the semiconductor substrate with the gate oxide film interposed therebetween. Equipped with a floating gate electrode,
The floating gate electrode is interposed between the discharge electrode and the injection electrode with an insulating layer interposed therebetween.
A semiconductor device having a layered electrode structure, characterized in that a protruding piece is formed on at least one of the electrodes, and the protruding piece forms an overlapping portion between the electrodes. Device.