JPS63180998U - - Google Patents

Info

Publication number
JPS63180998U
JPS63180998U JP1987073086U JP7308687U JPS63180998U JP S63180998 U JPS63180998 U JP S63180998U JP 1987073086 U JP1987073086 U JP 1987073086U JP 7308687 U JP7308687 U JP 7308687U JP S63180998 U JPS63180998 U JP S63180998U
Authority
JP
Japan
Prior art keywords
package
leads
semiconductor chip
semiconductor
meshing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987073086U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987073086U priority Critical patent/JPS63180998U/ja
Publication of JPS63180998U publication Critical patent/JPS63180998U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987073086U 1987-05-15 1987-05-15 Pending JPS63180998U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987073086U JPS63180998U (enExample) 1987-05-15 1987-05-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987073086U JPS63180998U (enExample) 1987-05-15 1987-05-15

Publications (1)

Publication Number Publication Date
JPS63180998U true JPS63180998U (enExample) 1988-11-22

Family

ID=30917108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987073086U Pending JPS63180998U (enExample) 1987-05-15 1987-05-15

Country Status (1)

Country Link
JP (1) JPS63180998U (enExample)

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