JPS63180120A - Cyclic processor in computer system - Google Patents

Abstract

PURPOSE:To improve the reliability of a computer system and also to ensure its general usefulness by using an execution managing device and outputting an AND between the managing information output and the execution timing output to process plural objects. CONSTITUTION:An execution managing device 3 supplies the greatest common measure of plural intervals obtained by an interval timer 2 as the timer value and divides the maximum interval value of a computer system by said timer value. Then the interruptions are applied to the device 3 from the timer 2 at every timer value in the form of the bit field having a size equivalent to the value obtained from said division. The AND is obtained at the time of the interruption between the control information output 121 given from an execution managing information table part 4 and the execution timing output 122 given from a bit pointer part 5. Then the processing parts 6-9 perform their processing actions only when the AND output 123 is equal to 1. Thus the control is possible just with a single timer 2 and the smooth processing is ensured within the device 3. Then the reliability of a computer system is improved together with its general usefulness.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a cyclic processing device in a computer system.

30 Summary of the Invention The present invention provides a cyclic processing device in a computer system, which includes: determining the greatest common divisor of a plurality of intervals; using this as a timer value; and dividing the longest value of the interval by the timer value; An execution management unit that executes and manages an interval using a bit field corresponding to the value obtained by this division (consisting of an execution management information table unit that instructs the execution management unit to command commands, and a bit pointer unit) This is intended to improve the reliability of the device and provide versatility.

C9 Prior Art Conventionally, in a cyclic processing device in a computer system, when there are a plurality of processing objects to be processed at different intervals, a plurality of interval timers have been provided which operate at each interval.

FIG. 4 shows a block diagram of such a cyclic processing device. In this figure, interval timers 50 to 53 are connected to respective processing units 55 to 53 via a timer management unit 54.
It is attached to 58. Interval timer 50-53
supplies timer outputs 100-103 to the timer management unit 54, and the timer management unit 54 supplies management information outputs 104-107 to processing units 55-58.

However, in such a conventional cyclic processing device, when the number of processing units increases, the timer management unit 54 must manage the increased number of processing units. Therefore, in the five-processing device, each timer output 100 to 103 is input to the timer management section 54 when each interval timer 50 to 53 is activated, which complicates the processing in the timer management section 8 (154) and reduces the reliability of the device. Furthermore, in the conventional cyclic processing device, the size of the bit field corresponding to the management information outputs 104 to 107 supplied to each processing section is smaller than the size of each timer output 100 to 107 output by the interval timers 50 to 53. Since it was uniquely determined by 103, it lacked versatility.

An object of the present invention is to provide a cyclic device in a computer system that improves the reliability of the device and is versatile.

E6 Means for Solving Problems As a means for solving the above problems, the present invention provides a cyclic processing device for a computer system that uses an interval timer to manage objects to be processed at a plurality of intervals. Find the greatest common divisor of the intervals, divide the longest interval value of the interval by the timer value of the interval timer and the timer value of the interval timer, and correspond to the value obtained by this division. an execution management device that executes and manages the interval using a bit field to be executed, an execution management information table section that supplies management information output to the execution management device, and a bit pointer section that supplies execution timing output to the execution management device. The execution management device is characterized in that it processes a plurality of processing targets by outputting a logical product of the management information output and the execution timing output.

21 Functions In the digital processing device, a plurality of processing targets are managed by one interval timer, thereby simplifying the processing of the execution management device and ensuring that the processing is carried out smoothly. Furthermore, in this device, the size of the pit field can be changed to provide versatility.

G. Example Next, the present invention will be explained in detail based on the example shown in mt diagrams to FIG.

FIG. 1 is a block diagram showing an embodiment of the cyclic processing device of the present invention. In this figure, reference numeral l is the cyclic processing device, and this cyclic processing special prize 1 operates by setting an interval timer 2. , this interval timer 2 has multiple intervals (for example, 5 seconds, 10 seconds, 30 seconds).

60 seconds) is found, and this is set as the timer value (5 seconds), which is connected to the execution management device. The execution management device 3 divides the longest ink-pulse interval value (60 seconds) in the computer system 2 by the timer value (5 seconds).

This device generates a pill field of a size corresponding to the value obtained by this division. Further, an execution management information table FAA and a bit pointer unit 5 are connected to the execution management device 3. Among these, the execution management information table section 4 is
For example, a memory consisting of the data array shown in FIG. The execution management information supplied from the execution management information table 4 to the execution management device 13 is the management information output 121. Further, the bit pointer unit 5 is a register consisting of the contents of the accumulator shown in FIG. 3, for example, and supplies an execution timing output 122 to the execution management device 3 with the same bit field size. In addition, in the cyclic processing device of this embodiment, when an interrupt is applied to the execution management device 3 by the interval timer 2, the management information output 121 output from the execution management report table 4 and the output from the bit pointer unit 5 are output. Logical AND with execution timing output (
AND).

Only when the logical product is 1, the processing of processing units 6 to 9 (5, 1
0,3 (J, 60 seconds processing) is executed.

Next, the operation of this embodiment will be explained.

First, the least significant digit accumulator of the bit pointer section 5 is set to 1, and the other accumulators are initialized to O.

Next, interval timer 2 is activated. Interval timer 2 uses multiple intervals (for example, 5 seconds,
Find the greatest common divisor (5 in this case) of 10 seconds, 30 seconds, 60 seconds) and use this as the Ta, Imma value (5 seconds).Also,
In the execution management device 3, the “interval timer 2 timer [
Divide the longest interval value (60 seconds) by (5 seconds), and make the bit field size corresponding to the value obtained by this division (60÷5=12 bits). Then, in the execution management device 3, the timer value (5 seconds) is set from the interval timer 2.
An interrupt is generated every time, and when this interrupt is generated, the execution management table F! ! The logical product (AND) of the W processing information output 121 from A4 and the execution timing output 122 from the bit pointer 8is5 is determined. Then, when the logical product output 123 of the execution management device 3 is "1", this cyclic processing is executed, and when the Mll horizontal product output 123rOJ, the program sequence is skipped by one and the program is advanced. That is, in this embodiment, if the instruction is in the n-th accumulator, the n+1 address is executed when the logical product output 123 is "1", and the n+2 address is executed when the logical product output 123 is "0". Execute. Therefore, for example, when executing the processing of the processing unit 6, calculate the AND of the management information output 121 (instruction of the processing unit 6 shown in FIG. 2) and the execution timing output 122 (instruction shown in FIG. 3), (001)+a(1
(in hexadecimal), it is determined that it is to be executed, and the processing unit 6
(5 seconds processing). Similarly, the processing unit 6 to
Perform step 9. When the processing of the processing unit 9 (60 seconds processing) is completed, the contents of the accumulator are shifted to the left and the contents of the accumulator are shifted to the left (002
),, to . Then, in the execution management device @3, an interrupt occurs again from the interval timer 2 after 5 seconds, and when the logical product of the management information output 121 and the execution timing output 122 is calculated in the same manner as above, it becomes (002)II, which is the execution target. It is determined that this is the case, and the processing of the processing unit 6 is executed. Next, the management information output 121 (processing s7 shown in FIG.
The logical AND of the execution timing output 122 (instruction shown in FIG. 3) is (000), s,
It is determined that it is not to be executed, and the process is skipped without being processed by the processing unit 7 (10 second process). Thereafter, the processing in the processing unit 8.9 is similarly skipped. After skipping the processing of the processing section 9, the contents of the accumulator of the bit pointer section 5 are shifted. In this processing device, the contents of the accumulator of the bit pointer section 5 can be shifted and used cyclically.

Therefore, according to the cyclic processing device of this embodiment, the processing target (interval) of the count can be managed by one interval timer 2, so that the processing in the execution management information 3 becomes smooth, and the device It is possible to avoid deterioration of reliability. Furthermore, in this embodiment, the size of the timer value and the bit field of the execution management information can be changed 415, so it is possible to provide versatility, and by sliding the execution management information, each process can be executed at each execution timing. It becomes easier to synchronize between departments.

H6 Effects of the Invention As described above, according to the present invention, a large number of execution targets can be managed by one interval timer, so processing within the execution management device becomes smooth and reliability of the device is improved. It is possible to eliminate deterioration. Further, in the present invention, the size of the bit field of the timer value and the execution pipe f@ information can be changed, so that versatility can be provided.

[Brief explanation of the drawing]

1 to 3 are diagrams showing an embodiment of a cyclic processing device in a computer system of the present invention, and FIG. 4 is a block diagram showing an example of a conventional cyclic processing device. 2...Interval timer, 3...Execution management information,
4... Execution management report table section, 5... Bit pointer section.

Claims (1)

[Claims] In a cyclic processing device in a computer system in which a plurality of execution targets are managed by an interval timer, the greatest common divisor of the intervals is determined, an interval timer whose timer value is this greatest common divisor, and an interval timer whose timer value is the timer value of the interval timer are calculated. an execution management device that divides the longest value of the interval and executes and manages the interval using a bit field of a size corresponding to the value obtained by this division; and an execution management device that supplies management information output to the execution management device. It consists of a management information table section and a bit pointer section that supplies an execution timing output to the execution management device, and the execution management device outputs and processes a logical product of the management information output and the execution timing output. A cyclic processing device in a computer system characterized by: