JPS63179559U - - Google Patents
Info
- Publication number
- JPS63179559U JPS63179559U JP6924487U JP6924487U JPS63179559U JP S63179559 U JPS63179559 U JP S63179559U JP 6924487 U JP6924487 U JP 6924487U JP 6924487 U JP6924487 U JP 6924487U JP S63179559 U JPS63179559 U JP S63179559U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- terminal
- operational amplifier
- input
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例による絶対値回路
を示す回路図、第２図は従来の絶対値回路を示す
回路図である。
１０１は入力端子、３Ａは演算増幅器、４Ａは
スイツチ制御器、５Ａはスイツチ、Ｒ８は第１の
抵抗、Ｒ９は第３の抵抗、Ｒ１０は第２の抵抗、
Ｒ１１は第４の抵抗、Ｒ１２は入力抵抗、Ｒ１３
はフイードバツク抵抗。なお、図中、同一符号は
同一、又は相当部分を示す。
FIG. 1 is a circuit diagram showing an absolute value circuit according to an embodiment of this invention, and FIG. 2 is a circuit diagram showing a conventional absolute value circuit. 101 is an input terminal, 3A is an operational amplifier, 4A is a switch controller, 5A is a switch, R8 is a first resistor, R9 is a third resistor, R10 is a second resistor,
R11 is the fourth resistor, R12 is the input resistor, R13
is the feedback resistance. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
間に互いに直列接続した第１の抵抗および第２の
抵抗と、上記入力端子と上記演算増幅器の正端子
との間に互いに直列接続した第３の抵抗および第
４の抵抗と、上記演算増幅器の負端子と出力端子
との間に接続したフイードバツク抵抗と、一端が
上記演算増幅器の正端子に他端がコモン電位に接
続された入力抵抗と、上記第１の抵抗および第２
の抵抗の接続中点または上記第３の抵抗および第
４の抵抗の接続中点のいずれかをコモン電位に切
換えるスイツチと、このスイツチを上記入力信号
の正負状態に応じて切換制御するスイツチ制御器
とを備えた絶対値回路。 a first resistor and a second resistor connected in series with each other between the input terminal of the input signal and the negative terminal of the operational amplifier; and a third resistor connected in series with each other between the input terminal and the positive terminal of the operational amplifier. a feedback resistor connected between the negative terminal and the output terminal of the operational amplifier; an input resistor having one end connected to the positive terminal of the operational amplifier and the other end connected to a common potential; the first resistor and the second resistor
a switch that switches either the connection midpoint of the resistor or the connection midpoint of the third resistor and the fourth resistor to a common potential, and a switch controller that controls switching of this switch depending on the positive or negative state of the input signal. Absolute value circuit with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6924487U JPS63179559U (en) | 1987-05-08 | 1987-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6924487U JPS63179559U (en) | 1987-05-08 | 1987-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179559U true JPS63179559U (en) | 1988-11-21 |
Family
ID=30909796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6924487U Pending JPS63179559U (en) | 1987-05-08 | 1987-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179559U (en) |
-
1987
- 1987-05-08 JP JP6924487U patent/JPS63179559U/ja active Pending