JPS63179263A - Phase reversal detecting circuit - Google Patents

Abstract

PURPOSE:To enable phase reversal detection and open phase detection by providing a means which resets the operation of a FF at the time of reversed-phase input and an open phase with a reset signal obtained by delaying a 2nd phase signal from a 2nd phase detecting means. CONSTITUTION:The output of a photocoupler PC1 is supplied to the clock pulse input terminal CK of the FF 1. The output of a photocoupler PC2, on the other hand, is supplied to a terminal A of a monostable multivibrator M1 through an inverter G2 and the output (e) of the monostable multivibrator M1 is supplied to a terminal CK of an FF 2. When there is a reversed-phase input, the phase of a phase signal (c) leads a phase signal (d) by 120 deg. and the reset signal (g) is at 'H' when the signal (c) rises. Therefore, the FF 1 does not latch a voltage +V even when inputting the signal (c) and a detection output (i) is still at 'L'. Further, when, for example, a T phase is open, an S-T phase voltage (b) is 0V, so the signal (d) is also held at 'L' as it is. The signal (g) which is the Q output of the FF 2 is at 'H' and the Q output of the FF 1 is still at 'L', so that the output (e) falls to 'L'.

Description

[Detailed description of the invention] (Field of invention) The present invention relates to a three-phase alternating current anti-phase detection circuit.

(Prior art and its problems) For example, when connecting a three-phase AC power source to a three-phase induction motor, if the power source is incorrectly connected, the motor may reverse, causing major trouble. Therefore, a three-phase alternating current anti-phase detection circuit is used to prevent such power supply connection errors. FIG. 7 shows an example in which an anti-phase detection circuit is used to prevent reverse rotation of a three-phase induction motor as described above. Each phase R, S, and T of the three-phase alternating current is connected to a three-phase induction motor M via an electromagnetic contactor.

An anti-phase detection circuit 10 is provided in parallel with the power input terminal of the royal induction motor M.

The configuration of such anti-phase detection circuit 10 is shown in FIG.

The R phase is connected to the LED anode terminal side of one photocoupler Pct, and the S phase is connected to the power source terminal side. The S phase is connected to the LED anode terminal side of the other photocoupler PC2, and the T phase is connected to the cathode terminal side.

The transistor output of the photocoupler PCI is applied to the D terminal of the D flip-flop FF, and the transistor output of the photocoupler PC2 is applied to the clock terminal of the D flip-flop FF. In addition, in the same figure, R
1-R4 represents a resistor for current limiting, and DI and D2 represent diodes for limiting input voltage.

Next, the operation of the anti-phase detection circuit having the above-described configuration will be explained in the ninth section.
This will be explained according to the figures and FIG.

Figure 9 shows the operating waveforms of each part when the S-T phase voltage is in a phase leading state with respect to the R-S phase voltage (assumed to be a positive phase state), and Figure 10 shows the operating waveforms of each part when the three-phase AC power supply is reversed. The operation waveforms of each part are shown when the R-3 phase voltage is connected to the S-T phase voltage and is in a phase leading state (in an anti-phase state).

First, in the normal phase state, when the R-3 phase voltage a shown in FIG. 9 (al) is input to the photocoupler PCI, the phase signal C as shown in FIG. On the other hand, by inputting the S-T phase voltage shown in Figure 9) to the photocoupler PC2, the phase signal is outputted from this photocoupler PC2 as shown in Figure 9+d). Since the phase signal C is at the 'HJ level at the falling edge of the 0th place signal d, in which the phase signal d having a phase difference of 120'' from C is output, the Q output e of the D flip-flop 1FF is at the 'HJ level. Become (9th
(see figure (e)), that is, when the three-phase AC is in positive phase, D
'HJ level is output from the flip-flop FF.

On the other hand, the waveforms of the R-3 phase voltage and the ST-phase voltage in the anti-phase state are shown in FIGS. 10(a) and 10(b).

At this time, the phase relationship between the phase signals c and d is opposite to the phase relationship in the normal phase state, as shown in FIG. Since the signal C is at the 'LJ level, the Q output e of the D flip-flop FF becomes the 'LJ level.

In this way, it can be determined from the state of the D flip-flop FF whether the three-phase AC power source is correctly connected to the three-phase induction motor M.

However, conventional anti-phase detection circuits
Although it is effective in determining out-of-phase, for example, one of the contacts of the electromagnetic contactor shown in Fig. 7 may cause a contact failure, resulting in a so-called open phase condition and causing the three-phase induction motor M to stop. For example, when the R phase is open, the phase signal C is always at the 'HJ level. Therefore, the 'HJ level is output from the D flip-flop FF, and it is erroneously determined that the three-phase AC power supply is normally connected.

(Object of the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an anti-phase detection circuit capable of not only anti-phase detection but also open phase detection. .

(Structure and Effects of the Invention) [Structure] In order to achieve the above object, the present invention provides a first method as means for detecting the phases of two input line voltages.
and a second phase detection means.

The first phase signal from the first phase detection means is given as a clock pulse to a flip-flop circuit that latches the set voltage. The second phase signal from the second phase detection means is given to the reset signal generation means. This reset signal generation means generates a reset signal based on delaying the second phase signal, and uses this reset signal to reset the operation of the flip-flop circuit when an anti-phase input and an open phase occur.

[Effect]

When the three-phase AC input is a positive phase input, the first phase signal operates the flip-flop, latches the set voltage, and inverts the output. On the other hand, when the three-phase AC input is in opposite phase, the flip-flop circuit is reset by the reset signal and remains in its initial state. If an open phase occurs such that the line voltage on either side becomes zero volts, the first
The flip-flop circuit remains in its initial state because either the phase signal is not output or the reset signal resets the flip-flop circuit. If a phase loss occurs such that the line voltages are in phase, the second phase signal is delayed by the reset signal generating means, so the first
A phase difference occurs between the phase signal and the second phase signal, and a reset signal is output based on this, thereby resetting the flip-flop circuit and maintaining its initial state.

〔effect〕

From the above, according to the present invention, not only anti-phase detection of three-phase AC input but also open phase detection can be performed.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram of an anti-phase detection circuit according to an embodiment of the present invention.

In this figure, the same reference numerals as in FIG. 8 indicate the same parts, so the explanation here will be omitted.

The photocoupler PC1 and the like constitute a first phase detection means for detecting the phase of the R-3 phase voltage a. The photocoupler PC2 etc. is a second photocoupler that detects the phase of the S-T phase voltage.
This constitutes the phase detection means. Such a phase detection means is not limited to a photocoupler, but may be configured using, for example, a transformer and a waveform shaper.

The output of the photocoupler Pct is applied to the clock pulse input terminal ck of the flip-flop circuit FFI via the inverter G1. Flip-flop circuit FFI is D-
It is a flip-flop, and a voltage +V is set at its D terminal. Hereinafter, the output of inverter G1 will be referred to as phase signal C.

On the other hand, the output of the photocoupler PC2 is applied to the A-satin of the mono multi-vibration brake M1 via an inverter G2. The mono multi-by-break M1 realizes a delay function included in the reset signal generating means. The delay time is set to 1/3 or less of the period (60 Hz) of the three-phase AC input. In this embodiment, the delay time is set to about 4 m5ec by the time constants of the resistor R5 and the capacitor C1. Hereinafter, the output of inverter G2 will be referred to as phase signal d.

The output e of the mono-multi-bi-break M1 is applied to the clock pulse input terminal ck of the flip-flop circuit FF2. The flip-flop circuit FF2 is a D-flip-flop circuit, and the 0 phase symbol d whose D terminal is set to a voltage +V is applied to the above-mentioned mono multivibrator M1 and is also applied to the flip-flop circuit via the inverter G3. It is applied to the reset terminal R of the pull-up circuit FF2. The output of the flip-flop circuit FF2 is applied to the reset terminal R of the flip-flop circuit FFI.

Then, the Q output of the flip-flop circuit FFI is given to the A terminal of the retriggerable mono multivibrator M2. Retriggerable mono multi-vibrake M2
The pulse width is set to more than one period of the three-phase AC input. In this embodiment, the pulse width is set to about 100 m5ec by the time constant of the resistor R6 and the capacitor C2. The Q output of the retriggerable mono-multi-bi-break M2 serves as a detection output for determining the positive phase, 2 anti-phases, and open phase of the 3-phase AC input.

Next, the operation of the embodiment having the above-described configuration will be explained with reference to FIGS. 2 to 6.

■In the case of positive phase input When the three-phase AC input is in positive phase (in this example, S-T
(When the phase voltage is in a leading state with respect to the R-3 phase voltage)
, R-3 phase voltage a have the phase relationship as shown in FIG.

Therefore, the phase signal d shown in FIG.
The waveform has a phase lead of 120 degrees with respect to the phase signal C shown in Figure (C1).

By applying this phase signal d to the mono multivibrator M1, the output e of the mono multivibrator M1 becomes a pulse delayed by about 4 m5ec from the rising edge of the phase signal d, as shown in Fig. 2 (61). By applying this output e to the flip-flop circuit FF2, the flip-flop circuit FF2 is triggered by the rising edge of the output e and latches the voltage +V.

On the other hand, the phase signal d is inverted by the inverter G3, and the second
A signal f shown in FIG. 3(f) is applied to the flip-flop circuit FF2. As a result, the flip-flop circuit FF2 is reset by the signal f, and its output (reset signal g) becomes as shown in FIG.

By the way, the flip-flop circuit FFI receives the phase signal C
The voltage +V is latched by inputting the voltage +V, and then it is reset by the rising edge of the reset signal g. Therefore, the Q output of the flip-flop circuit FFI becomes a pulse synchronized with the phase signal C as shown in FIG. When this Q output is input to the retriggerable mono multivibrator M2, the pulse width of the retriggerable mono multivibrator M2 is set to be longer than one cycle of the three-phase AC input, so the Q output ( The detection output i) is 'HJ' as shown in Fig. 2 (1).
become the level. In this way, when the three-phase AC input is a positive phase input, the detection output l becomes 'HJ level.

In the case of 0 anti-phase input, the operating waveforms of each part in this case are shown in Fig. 3 (al to il). The phase is 120 degrees ahead of the phase signal d.Therefore, at the rise of the phase signal C, the reset signal g is at H level.Therefore, the flip-flop circuit FFI is
Since the voltage +V is not latched even when the phase signal C is input, the detection output i maintains the 'LJ level. in this way,
In the case of anti-phase input, the detection output i becomes 'LJ level.

■In the case of T-phase open phase The operating waveforms of each part in this case are shown in Figure 4 (al to (il). In the case of T-phase open phase, the S-T phase voltage is shown in Figure 4 (false). Since the voltage becomes zero volts, the phase signal d also remains at the 'LJ level as shown in dl in the same figure.Therefore, the reset signal g, which is the output of the flip-flop circuit FF2, Therefore, as shown in the figure (ttl), the Q output of the flip-flop circuit FFI remains at the 'LJ level, and the flip-flop circuit FFI remains at the 'LJ level' as shown in the figure (ttl). As shown in 11, the detection output l is 'LJ
become the level. In this way, in the case of T phase open phase, the detection output i
becomes 'LJ level.

■In the case of R-phase open phase The operating waveforms of each part in this case are shown in Figure 5 (al~(11). In the case of R-phase open phase, the R-3 phase voltage a is shown in Figure 5 (al~(11).
Since the voltage becomes zero volts as shown in (a), the phase signal C also remains at the 'LJ level as shown in (e) of the figure. Therefore, since the flip-flop circuit FFI does not latch the voltage +V, its Q output becomes 'LJ level as shown in the figure (hl), and the detection output i also goes to 'LJ level as shown in figure (1). become.

In this way, when the R phase is open, the detection output l becomes the 'LJ level.

■In the case of S phase open phase The operating waveforms of each part in this case are 6th rgJ+a11~(1
) is shown. In the case of S phase open phase, current flows between T and R phases, so as shown in Figure 1al and (bl), R-
The 5-phase voltage a and the S-T phase voltage S are almost in phase,
Therefore, as shown in the same figure (C1, Tdl), the phase signal c,
d also becomes almost in phase. From this, it is understood that a detection output cannot be obtained by simply inputting the phase signals c and d to the flip-flop circuit FF as in the conventional circuit shown in FIG. In this embodiment, the reason why the mono-multi-bi-break M1 is provided to delay the phase signal d is to enable open-phase detection of the S phase.

That is, as the phase signal d is delayed by the mono multivibrator M1, the falling timing of the reset signal g is faster than the rising timing of the phase signal d of the mono multivibrator M1, as shown in the figure (illustration). It is delayed by the delay time.Therefore, at the rise of the phase signal C, the reset signal g is 'HJ level,
That is, since the flip-flop circuit FFI is in the reset state, its Q output is r L as shown in the figure (hl).
J level, the detection output i as shown in the figure (11)
It will also be at LJ level. In this way, even in the case of S-phase open phase, the detection output i becomes 'LJ level.

As described above, in the case of positive phase input, the detection output i is at the 'HJ level, and in the case of anti-phase and open phase input, the detection output i is at the 'L' level.
Since it is at the J level, according to this embodiment, not only the reverse phase of the three-phase AC input but also the open phase can be detected.

In addition, in the above-mentioned embodiment, the output of the retriggerable mono multi-vibration brake M2 is in positive phase.

Antiphase and phase loss are detected, but as is clear from the above explanation, it is possible to determine this also from the output of the flip-flop circuit FF1, so in the present invention, the retrigger pull mono multi-bi break M2 is not necessarily used. It's not what's needed.

Furthermore, in the above-described embodiment, the case where the S-T phase voltage is in a phase leading state with respect to the R-8 phase voltage is defined as a positive phase input, and the opposite state is defined as a negative phase input. The case where the R-3 phase voltage is in a phase leading state with respect to the S-T phase voltage may be regarded as a positive phase input, and the opposite state may be regarded as a negative phase input.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an anti-phase detection circuit according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of each part of the embodiment at the time of positive phase input, and FIG. 3 is an anti-phase input FIG. 4 is an operating waveform diagram of each part of the embodiment in T-phase open phase holding, FIG. 5 is an operating waveform diagram of each part in the above embodiment in R-phase open phase hold, FIG. 6 is an operation waveform diagram of each part of the embodiment in the S-phase with an open phase, FIG. 7 is an explanatory diagram showing the usage state of the anti-phase detection circuit according to the conventional example and the embodiment, and FIG. 8 is the conventional example. FIG. 9 is an operating waveform diagram of each part of the conventional example when inputting a positive phase, and FIG. 1O is an operating waveform diagram of each part of the conventional example when inputting a negative phase. Pct, PC2...Photocoupler, FFI, FF2・
...Flip-flop circuit, Ml...mono multivibrator, M2...retrigger pull mono multivibrator.

Claims (1)

[Claims] (1) A first phase detection means for detecting the phase of the first line voltage of the three-phase AC input; and a second phase detection means for detecting the phase of the second line voltage of the three-phase AC input. and a flip-flop circuit that latches a set voltage by being given the first phase signal from the first phase detection means as a clock pulse, and a second phase signal from the second phase detection means. An anti-phase detection circuit comprising reset signal generating means for resetting the operation of the flip-flop in the event of anti-phase input and phase loss, using a reset signal obtained based on the delay.