JPH08308246A - Pwm control circuit for neutral point clamp type inverter - Google Patents

Abstract

PURPOSE: To guarantee the minimum ON time and the minimum OFF time and to eliminate the damage of an element by providing a command value 0 vicinity detector for detecting that a voltage command value becomes near 0, and a circuit for forcedly fixing the switching mode of PWM control according to a command value 0 vicinity detection signal. CONSTITUTION: The PWM control circuit for a neutral point clamp type inverter compares a command value 0 vicinity detector 11 for detecting that a voltage command value VS becomes near 0, and circuits 41 to 44 for forcedly fixing the switching mode of PWM control according to a command value 0 vicinity detection signal. Thus, since the 0 vicinity of the value VS is detected so that the switching mode is fixed, the generation of the output voltage of the shorter time than the minimum ON time and the minimum OFF time generated near the 0 of the value VS is eliminated, and the damage of the element generated if the minimum ON time and the minimum OFF time are not satisfied is obviated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for a neutral point clamp type inverter that guarantees a minimum on time and a minimum off time when the neutral point clamp type inverter is controlled by a triangular wave carrier comparison PWM.

[0002]

2. Description of the Related Art FIG. 1 shows one phase of a main circuit of a neutral point clamp type inverter. This inverter has a DC power supply P,
Switching elements T1 to T4 are connected in series between N, between the neutral point O of the DC power source and the connection point of the elements T1 and T2, and between the connection point of the elements T3 and T4 and the neutral point O, respectively. The diodes D1 and D2 are connected, and the connection point of the elements T2 and T3 is used as the output point U.

In this neutral point clamp type inverter, when control is performed by a triangular wave (including metal teeth) carrier comparison method, normally two carriers (upper carrier and lower carrier) A1 and A2 as shown in FIG. To determine the switching mode of the inverter. When the command value V _S is larger than the upper carrier A1, the output voltage V _U is H
When the command value V _S is lower than the level, the lower carrier A2, an L level voltage is output, and when the command value V _S is between the upper carrier A1 and the lower carrier A2, an O level voltage is output.

This inverter theoretically applies only half the voltage of the DC power supply voltage to the main circuit switching element. Therefore, when the same element is used, the output voltage is doubled when compared with a general voltage source inverter. There is an advantage that the breakdown voltage of the element can be halved if the inverter can be configured and the output capacitance is the same.

[0005]

When the inverter is PWM-controlled using two carriers as described above, when the angle of the carrier and the command value cross each other, the switching mode is changed for an extremely short time. Become. As a result, there occurs a case where the minimum on-time and the minimum off-time cannot be satisfied as shown in FIG. This causes problems such as device breakdown.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a neutral point clamp type inverter capable of guaranteeing a minimum on-time and a minimum off-time. It is to provide a control method.

[0007]

In order to achieve the above object, the present invention provides a PWM control circuit for a neutral point clamp type inverter, in which a voltage command value near O is detected to detect that the voltage command value is near O. A detection circuit and a circuit for forcibly fixing the switching mode of the PWM control by the detection signal near the command value O are provided.

[0008]

Since the vicinity of O of the voltage command value is detected and the switching mode is fixed, the minimum ON time generated near O of the voltage command value and the output voltage of a time shorter than the minimum ON time are not generated. Minimum on-time and minimum off-time are guaranteed. Therefore, damage to the switch element that occurs when the minimum on time or the minimum off time is not satisfied is eliminated.

[0009]

Embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a PWM control circuit of the neutral point clamp type inverter (FIG. 1) described in the prior art.

In FIG. 2, 11 is a command value O for detecting whether or not the sine wave voltage command V _S of the inverter is near O.
In the vicinity detection circuit, the voltage V _B1 of the power supplies E _O1 and E _O2 close to 0,
Comparators 13 and 14 for comparing V _B2 with the voltage command value V _S ,
It is composed of a logic circuit 15 which outputs the output signals of the comparators 13 and 14 as a logical product.

Reference numerals 21 and 22 are triangular wave generators for outputting the upper carrier and the lower carrier (FIG. 4). Reference numerals 23 and 24 are used for comparing the upper carrier and the lower carrier with the command value V _S to determine the upper PW.
PWM comparator for outputting M signal and lower PWM signal, 2
Reference numeral 5 denotes a logical product circuit for passing the output signal of the comparator 24 on condition that there is no output from the comparator 23. Reference numeral 31 denotes a signal from the logical product circuit 15 input to the input terminal D and a signal from the logical product circuit 25. A D-type flip-flop (FF) circuit input to the second input terminal, 33 and 34 are logic inversion circuits that invert the output signals of the comparators 23 and 24, and 41 is a condition that there is no signal from the FF circuit 31. A first gate circuit that gate-drives the switching element T1 of the inverter (FIG. 1) when there is a signal from the comparator 23, 42 is the logical sum of the signals from the FF circuit 31 and the comparator 24, and the switching element T2
Second gate circuit for driving the gate of the FF circuit 3
1 and a third gate circuit for driving the gate of the switching element T3 with the logical sum of signals from the logical inversion circuit 33, 4
Reference numeral 4 is a fourth gate circuit which drives the gate of the switching element T4 when there is a signal from the logic inverting circuit 34 on condition that there is no output from the FF circuit 31.

Next, the operation of the embodiment will be described with reference to FIG.

When the voltage command value V _S is higher than the voltage V _B1 , the output signal of the comparator 13 is L and the output signal of the AND circuit 15 is also L, so the output of the FF circuit 31 is L.
Is. Therefore, the switching elements T2 and T3 are driven by the output signal of the comparator 24 and the inverted signal of the output signal of the comparator 23 via the gate circuits 42 and 43, and the switching element 41 is driven by the comparator 23 via the gate circuit 41.
It is driven by the PWM signal from.

Therefore, at this time, the output voltage H is output as shown in FIG. This output voltage H is the same as the output voltage H of the part that satisfies the minimum on-time in FIG. 4 of the related art.

At this time, since the output signal of the comparator 24 is H and the output signal of the logic inverting circuit 34 is L, the gate circuit 44 does not output and the switching element 44 does not output.
Is off.

The voltage command value V _S decreases and the voltage V near 0
_When entering between _S1 and V _S2 , the output signals of the comparators 13 and 14 both become H, so the output signal from the AND circuit 15 also becomes H.
Becomes

On the other hand, the logical product circuit 25, when the command value V _S is positive, when the PWM signal from the comparator 23 is L and the signal of the comparator 24 is H, and when the command value V _S is negative, Comparator 24
The output signal becomes H when the PWM signal from is H.

Therefore, when the AND circuit 15 detects the zero point of the command value V _S , the FF circuit 31 outputs when the signal output from the AND circuit 25 rises immediately after that, and the output of the AND circuit 15 When the signal becomes L, the output disappears when the signal output from the AND circuit 25 rises immediately after that.

Therefore, when the command value V _S approaches the zero point, the FF circuit 31 outputs and the gate circuits 41 and 44 are forcibly turned off, and the switch elements T1 and T4 are not turned on. This guarantees a minimum on time and a minimum off time.

The gate circuits 42 and 43 are turned on by the output of the FF circuit 31 while the gate circuits 41 and 44 are forcibly turned off.

According to the embodiment, when the command value V _S is within the range of the voltages V _B1 and V _B2 , the switching mode is fixed so as not to output an output that does not satisfy the minimum on time and the minimum off time. Therefore, an error may occur with respect to the command value, but since the error voltage is output only for a period shorter than the minimum on time and the minimum off time,
It has little effect on accuracy.

Further, in the embodiment, the detection circuit 11 causes the command value O
After detecting the vicinity, through the FF circuit 31, the gate circuit 41
However, the present invention is not limited to this because the reason why the FF circuit 31 is used is to eliminate the influence of noise when the vicinity of the command value O is detected.

[0023]

Since the present invention is configured as described above, it is possible to fix the switching mode in which an O level is output near the voltage command value O of the inverter. Therefore, there is no case where the minimum on-time and the minimum off-time of switching cannot be satisfied, and the switch element is not destroyed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one phase of a main circuit of a neutral point clamp type inverter.

FIG. 2 is a PWM control circuit diagram according to the embodiment.

FIG. 3 is a waveform diagram illustrating the operation of the embodiment.

FIG. 4 is a waveform diagram illustrating the operation of a conventional example.

[Explanation of symbols]

 11 ... Command value O vicinity detection circuit 13, 14 ... Command value O vicinity detection comparator 23, 24 ... Upper and lower PWM comparator 31 ... Flip-flop (FF) circuit 41-44 ... Gate circuit T1-T4 ... Switching Element D1, D2 ... Diode for neutral point clamp

Claims (1)

[Claims] 1. A PWM control circuit for a neutral point clamp type inverter: a command value O vicinity detection circuit for detecting that a voltage command value is near O, and a PWM control switching mode by a command value O vicinity detection signal. A PWM control circuit for a neutral point clamp type inverter, which is provided with a circuit for forcibly fixing and for ensuring a minimum on time and a minimum off time.