JPS63177586A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPS63177586A
JPS63177586A JP62009542A JP954287A JPS63177586A JP S63177586 A JPS63177586 A JP S63177586A JP 62009542 A JP62009542 A JP 62009542A JP 954287 A JP954287 A JP 954287A JP S63177586 A JPS63177586 A JP S63177586A
Authority
JP
Japan
Prior art keywords
hole
circuit
circuit board
circuits
conductive connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62009542A
Other languages
Japanese (ja)
Other versions
JPH0724334B2 (en
Inventor
川本 峰雄
捷夫 菅原
敢次 村上
昭雄 高橋
奈良原 俊和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62009542A priority Critical patent/JPH0724334B2/en
Publication of JPS63177586A publication Critical patent/JPS63177586A/en
Publication of JPH0724334B2 publication Critical patent/JPH0724334B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は各種電子機器に用いられるプリント配線板、モ
ジュール配線板、セラミック配線板など回路板の表裏回
路間、内層回路間、又は表裏回路と内層回路との間の導
通接続をする導通接続孔の構造に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to circuit boards used in various electronic devices, such as printed wiring boards, module wiring boards, and ceramic wiring boards, between front and back circuits, between inner layer circuits, or between front and back circuits. This invention relates to the structure of a conductive connection hole that provides conductive connection with an inner layer circuit.

〔従来の技術〕[Conventional technology]

従来、上記のような各種回路板の表裏回路間の接続、内
層回路間の接続、表裏回路と内層回路との間の接続はプ
レス、ドリル、プラズマ、光(例えばレーザー)等で回
路板にスルーホール(孔)をあけ、この孔内壁に化学メ
ッキ、又は化学メッキと電気メッキを併用して達成して
いた。また、これらメッキを行った後、異種金属の半田
などを充填したものもある。また、スルーホールにメッ
キを行なわず、スルーホールに導体線などを挿入してそ
の両端を回路に半田で固定するもの、ハトメピンを差し
込むもの、導電性ペーストやペレットを充填するもの(
特開昭6l−100999)がある。
Conventionally, connections between the front and back circuits of various circuit boards, connections between inner layer circuits, and connections between front and back circuits and inner layer circuits of the various circuit boards mentioned above were made through the circuit board using a press, drill, plasma, light (e.g. laser), etc. This was accomplished by drilling a hole and using chemical plating or a combination of chemical plating and electroplating on the inner wall of the hole. In addition, after performing these platings, there are also products that are filled with solder or the like of a dissimilar metal. In addition, there are also cases where the through hole is not plated and a conductor wire is inserted into the through hole and both ends are fixed to the circuit with solder, eyelet pins are inserted, and conductive paste or pellets are filled (
There is a Japanese Patent Application Publication No. 61-100999).

従来の各種の導通接続孔の断面を示したのが第4図の囚
〜fGlである。第4図の^及びの)は、表裏回路2の
導通接続孔(スルーホール)3の孔内壁にのみメッキ膜
を形成したものを示す。これらはの)の内層回路同志の
接続孔が樹脂で埋っていることを除き、表裏回路間の、
及び表裏回路と内層回路間の導通接続孔が空洞釦なって
いるのが特徴である。
The cross-sections of various conventional conductive connection holes are shown in FIG. 4 and 4) show a case in which a plating film is formed only on the inner wall of the conductive connection hole (through hole) 3 of the front and back circuits 2. Except for the connecting holes between the inner layer circuits (of these), which are filled with resin, there are no connections between the front and back circuits.
The feature is that the conductive connection hole between the front and back circuits and the inner layer circuit is a hollow button.

(C)はメッキで導通化した孔に、更に異種金属の半田
や導電性ペーストを充填したものを示す。の)は孔内壁
にメッキを行なわず、各々ハトメビンを挿入したもの、
■は孔に導体線を挿入してその両端を半田で表裏回路に
固定したもの、■は導電性ペースト又はペレットを孔に
挿入したものを示す0(Qは孔内壁にメッキ膜を形成し
た後、導電性ペースト又はペレットを挿入したものを示
す。
(C) shows a hole made conductive by plating and filled with solder of a different metal or conductive paste. ) is the one in which the inner wall of the hole is not plated and each eyelet is inserted,
■ indicates that a conductor wire is inserted into the hole and its both ends are fixed to the front and back circuits with solder; ■ indicates that a conductive paste or pellet is inserted into the hole; , indicates a conductive paste or pellet inserted.

第5図は従来の導通接続孔を有する回路板に電子部品を
搭載する状態を示した図である。第5図囚は導通接続孔
より部品固定用のランドを引き出し、その上に部品4の
接続バンプ5を固定した状態を示す。第5図の)は導電
性ペレット上に部品4の接続バング5を固定した状態を
示す。
FIG. 5 is a diagram showing a state in which electronic components are mounted on a conventional circuit board having conductive connection holes. FIG. 5 shows a state in which a component fixing land is pulled out from the conductive connection hole, and the connecting bump 5 of the component 4 is fixed onto it. 5) shows a state in which the connecting bang 5 of the component 4 is fixed on the conductive pellet.

〔発明が解決しようとすら問題点〕[Problems that the invention does not even try to solve]

近年、回路板は高密反部品実装のため、微細回路化が進
み、且つその配線密式の向上が行なわれている。具体的
には回路@/間隔が0.1 / 0.1 tax〜0.
06 / 0.06 mまで高められている。このため
表裏回路間、内層回路間、又は表裏回路と内層回路間と
の導通接続孔もφ0.3〜0.1mまで実用化され、一
部には≠0.1H以下の導通接続孔が試作されている。
In recent years, due to the high-density anti-component mounting of circuit boards, the miniaturization of circuits has progressed, and the wiring density has been improved. Specifically, the circuit@/interval is 0.1/0.1 tax~0.
06/0.06 m. For this reason, conductive connection holes between front and back circuits, between inner layer circuits, or between front and back circuits and inner layer circuits have been put into practical use with a diameter of 0.3 to 0.1 m, and in some cases, conductive connection holes with a diameter of ≠0.1H or less have been made as prototypes. has been done.

このような高密度微細回路の回路板に於て、前述した構
造の従来の導通接続孔では以下のように種々の問題が発
生する。
In circuit boards with such high-density microcircuits, the conventional conductive connection holes having the above-described structure cause various problems as described below.

孔内壁にのみメッキを形成するものでは、部品搭載時の
熱によって、メッキ膜にクラックが発生しやすい。半田
などをスルーホールに充填したものは、この半田充填時
の熱によってメッキ膜にクラックが発生しやすい。これ
は、メッキ膜を孔内壁にのみ形成している(孔内が空洞
である)、ため、信頼性に乏しいことを意味している。
In the case where plating is formed only on the inner wall of the hole, cracks are likely to occur in the plating film due to the heat generated when components are mounted. When through-holes are filled with solder or the like, cracks are likely to occur in the plating film due to the heat generated during filling with solder. This means that the plating film is formed only on the inner wall of the hole (the inside of the hole is hollow), and therefore reliability is poor.

従って、部品を直接、札止に固定できず、部品固定用の
回路(−)ンド)を孔から引き出す必要があった。この
ため、回路を微細化しても、ランドを設けることによっ
て、その微細回路の配線密度を向上させることができな
い問題があった。この問題は、孔内壁にメッキを行なわ
ないで、導体線を挿入してその両端を半田で固定するも
の、ハトメビンを差し込むものでも同様である。特に上
記の導体線を挿入して半田で固定するもの、ハトメビン
を差し込むものでは、内層回路と該導体線又はハトメビ
ンとの接続が良好でないという問題もある。
Therefore, the component could not be directly fixed to the bill holder, and it was necessary to pull out the circuit (-) for fixing the component through the hole. For this reason, even if the circuit is miniaturized, there is a problem in that the wiring density of the microcircuit cannot be improved by providing lands. This problem is the same even when the inner wall of the hole is not plated and a conductor wire is inserted and its both ends are fixed with solder, or when an eyelet is inserted. In particular, in the case where the conductor wire is inserted and fixed with solder or the eyelet hook is inserted, there is a problem that the connection between the inner layer circuit and the conductor wire or eyelet hook is not good.

一方、特開昭61−100999号のように、孔内壁の
メッキ膜の有無にかかわらず導電性ペレットを充填する
方法は、部品を該札止に直接固定できるため、高密度部
品実装が可能となるが、しかし、この導電性ペレットが
金属と樹脂とからなり、ポンチ、プレス等で孔に挿入す
るものであるため、該孔が−0,1m以下では十分に充
填されないので、孔径が≠0.3 tm以上を必要とし
、従って実質的に微細回路の配線密度を向上させる上で
障害となっていた。
On the other hand, the method disclosed in JP-A-61-100999, in which conductive pellets are filled with or without a plating film on the inner wall of the hole, enables high-density component mounting because components can be directly fixed to the tag. However, since this conductive pellet is made of metal and resin and is inserted into a hole using a punch, press, etc., if the hole is less than -0.1 m, it will not be sufficiently filled, so if the hole diameter is ≠0. 3 tm or more, and therefore has been an obstacle to substantially improving the wiring density of fine circuits.

本発明は上記従来の問題を解決し、配線密度の向上およ
び高密度部品実装を可能にすることを目的とする。
It is an object of the present invention to solve the above-mentioned conventional problems and to enable improved wiring density and high-density component mounting.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、回路板の表裏回路間、内層回路間又は表裏
回路と内層回路との間の導通接続孔全体が、これら回路
の金属と一体の且つこれら回路の金属と同一の金属で完
全に充填されていることによって達成される。
The above purpose is to completely fill the entire conductive connection hole between the front and back circuits of the circuit board, between the inner layer circuits, or between the front and back circuits and the inner layer circuit with a metal that is integral with the metal of these circuits and is the same as the metal of these circuits. This is achieved by what is being done.

〔実施例〕〔Example〕

本発明の実施形態の一例を第1図、第2図および第3図
をもって説明する。第1図の囚は両面回路板の場合、(
6)は多層回路板の場合の断面図である。第2図の囚〜
(6)は孔部分の回路の平面図である。第1図の囚及び
(2)は、絶縁板10両面及び内層に回路2が配線され
、導通接続孔3が回路と一体の且つ同一金属で充填され
ている状態を示す。
An example of an embodiment of the present invention will be described with reference to FIGS. 1, 2, and 3. In the case of a double-sided circuit board, the prisoner in Figure 1 is (
6) is a sectional view of a multilayer circuit board. Prisoner in Figure 2
(6) is a plan view of the circuit in the hole portion. 1 and (2) show a state in which the circuit 2 is wired on both sides and the inner layer of the insulating plate 10, and the conductive connection hole 3 is integrated with the circuit and filled with the same metal.

第2図の囚及び(6)は導通接続孔3の部分にランドが
ない実施例を示し、これは孔と孔との間隔を狭めること
ができ、高密度微細回路を形成できる例である。特に導
通接続孔が160.1 tea以下の場合、回路幅と間
隔とを各々0.1 m幅以下で配線することができる。
2 and (6) show an embodiment in which there is no land in the portion of the conductive connection hole 3, and this is an example in which the distance between the holes can be narrowed and a high-density microcircuit can be formed. In particular, when the conductive connection hole is 160.1 tea or less, wiring can be performed with a circuit width and an interval of 0.1 m or less, respectively.

第2図(0〜@は従来のように、導通接続孔にランドを
設けた実施例を示す。本発明では、第1図及び第2図に
示すように、導通接続孔を回路と一体の且つ同一金属で
充填することによって、第3図に示すように、部品4の
接続バンプ5を直接、該札止に固定することができ、微
細回路の配線密度の向上と、高密度部品実装の両立が達
成できる。
Fig. 2 (0 to @ show an embodiment in which a land is provided in the conductive connection hole as in the conventional case. In the present invention, as shown in Figs. 1 and 2, the conduction connection hole is integrated with the circuit. In addition, by filling with the same metal, the connection bumps 5 of the components 4 can be directly fixed to the tag as shown in FIG. 3, thereby achieving both improved wiring density of fine circuits and high-density component mounting. can be achieved.

本発明において、導通接続孔を回路と同一金属で完全に
充填する方法としては、化学メッキ法、化学メッキと電
気メッキとの併用法、熱溶解法、プラズマ法、スパッタ
法など、多くの公知の方法が適用できる。これらは、使
用する絶縁板の種類、回路及び導通接続孔の充填金属の
種類及び孔の寸法によって選択される。これらの方法の
うち、孔を充填する技術面、作業面の容易性、量産性(
歩留シ、コスト)等の産業上の利用価値の面からは化学
メッキ法、化学メッキと電気メッキの併用法、熱溶融法
の王者が好ましい。以下、この王者について概要説明す
る。
In the present invention, there are many known methods for completely filling the conductive connection hole with the same metal as the circuit, such as chemical plating, a combination of chemical plating and electroplating, thermal melting, plasma, sputtering, etc. method can be applied. These are selected depending on the type of insulating plate used, the type of filling metal for the circuit and conductive connection hole, and the size of the hole. Among these methods, the technical aspects of filling the holes, ease of operation, mass production (
From the viewpoint of industrial utility value (yield, cost), etc., chemical plating, a combined method of chemical plating and electroplating, and a thermal melting method are preferred. Below is an overview of this champion.

化学メッキ法は、各種絶縁板又は銅等の金属箔を張った
絶縁板に穴をあけた後、化学メッキ反応の触媒となる金
属(Pd、 Au、 Cu、 Ni等)を表面及び孔内
壁に付着させ、次にCu、Ni等の化学メッキを行う方
法である。回路形成は、全表面に化学メッキをした後、
その上にフォトレジストを形成し、次に写真法によって
回路パターンを描画し、回路以外の7オトレジストを除
去し、更に露出した化学メッキ膜及び金属箔をエツチン
グ除去し、最後に回路上の7オトレジストを除いて、完
成する。別の回路形成法としては、初めに回路形成部以
外のところへメツキレシストを形成し、回路形成部分へ
化学メッキを行って回路を形成するフルアディティブ法
を適用することもできる。即ち、化学メッキ法は回路及
び導通接続孔を化学メッキ膜だけで形成するものである
The chemical plating method involves drilling holes in various types of insulating plates or insulating plates covered with metal foil such as copper, and then applying metals (Pd, Au, Cu, Ni, etc.) that act as catalysts for chemical plating reactions to the surface and inner walls of the holes. This is a method in which the metal is deposited and then chemically plated with Cu, Ni, etc. For circuit formation, after chemically plating the entire surface,
A photoresist is formed on it, then a circuit pattern is drawn by photography, the 7 photoresists other than the circuit are removed, the exposed chemical plating film and metal foil are etched away, and finally the 7 photoresists on the circuit are removed. Completed except for. As another circuit forming method, it is also possible to apply a full additive method in which a metal resist is first formed in areas other than the circuit forming part, and then chemical plating is performed on the circuit forming part to form the circuit. That is, the chemical plating method forms circuits and conductive connection holes using only a chemical plating film.

化学メッキと、パ電気メッキの併用法は、初めに前述の
化学メッキを薄くつげ、次に化学メッキと同一金属の電
気メッキで厚く形成する方法である。
The combined use of chemical plating and electroplating is a method in which the aforementioned chemical plating is first applied thinly, and then a thick layer is formed using electroplating of the same metal as the chemical plating.

回路形成法としては、電気メツキ終了後に、フォトレジ
ストを形成し、前述の化学メッキ法と同様にエツチング
で回路を形成する方法と、化学メッキの後に回路形成部
以外に7オトレジストを形成し、孔内壁と回路を電気メ
ッキで厚くシ、その後フォトレジストを除去して露出し
た化学メッキ膜及び下地金属箔をエツチング除去する方
法を挙げることができる。
The circuit formation method is to form a photoresist after electroplating and form the circuit by etching in the same way as the chemical plating method described above, or to form a photoresist in areas other than the circuit formation area after chemical plating and to form holes. An example of this method is to thicken the inner wall and circuit by electroplating, then remove the photoresist, and then remove the exposed chemically plated film and underlying metal foil by etching.

熱溶解法は金属箔を張った各種セラεツク板を用い、孔
をあけた後、金属箔と同一金属のボールを札止に設置し
、金属の溶融温度以上に高められた電気炉にて金属箔及
び金属ボールを溶解して孔内を充填すると同時に一体化
せしめ、次にエツチングで回路以外の金属を除去して回
路を形成する方法である。この方法で使用する金属ボー
ルは孔の体積以上のものを用いることは勿論である。金
属箔は孔をあけた後、メッキで形成しても良い。
The thermal melting method uses various types of ceramic plates covered with metal foil, and after making holes, a ball made of the same metal as the metal foil is placed on a billboard, and the metal is melted in an electric furnace heated to a temperature higher than the melting temperature of the metal. This is a method in which the foil and metal balls are melted to fill the hole and are simultaneously integrated, and then etched to remove metal other than the circuit to form the circuit. Of course, the metal ball used in this method must have a volume larger than that of the hole. The metal foil may be formed by plating after making holes.

絶縁板としては、紙、ガラスクロス、アラミド繊維など
にフェノール、エポキシ、ポリイミドなどの有機樹脂を
含浸して積層接着したもの、各種セラミック材、金属板
を有機樹脂で包んだもの、更に、これら各種絶縁基板同
志を接合したものなどが挙げられ、本発明はそのいずれ
に限定されるものではない。一方、絶縁板に孔をあける
方法は、プレス、ドリル、プラズマ、溶融法、レーザー
、化学処理など公知の方法を、絶縁板の種類と目的とす
る孔径に応じて適用できる。更に、上面よりみた孔の形
状は円、円の変形、多角形及びこれらの変形であっても
良い。一方、孔の断面形状は、立方体、三角すい、つつ
み状、たいこ状などであっても良い。
Insulating plates include paper, glass cloth, aramid fibers, etc. impregnated with organic resins such as phenol, epoxy, and polyimide and laminated and bonded, various ceramic materials, metal plates wrapped in organic resin, and various other types. Examples include those in which insulating substrates are bonded together, and the present invention is not limited to any of them. On the other hand, as a method for making holes in the insulating plate, known methods such as pressing, drilling, plasma, melting, laser, and chemical processing can be applied depending on the type of the insulating plate and the intended hole diameter. Further, the shape of the hole viewed from the top surface may be a circle, a modification of a circle, a polygon, or a modification thereof. On the other hand, the cross-sectional shape of the hole may be a cube, a triangular pyramid, a cone, a cylindrical shape, or the like.

回路を形成する金属及び導通接続孔を充填する金属とし
ては銅、ニッケル、金、銀、白金、スズ、鉛、3 ハル
ト、タングステン、モリブデン、ニオブ、パラジウム、
笈びこれらの合金が挙げられ、本発明はこれらのいずれ
に限定されるものではない0 以下、本発明を実施例を具体的に説明する。
The metals forming the circuit and the metals filling the conductive connection holes include copper, nickel, gold, silver, platinum, tin, lead, 3-Hart, tungsten, molybdenum, niobium, palladium,
Examples include alloys thereof, and the present invention is not limited to any of these.Hereinafter, the present invention will be specifically explained with reference to Examples.

実施例1 両面に約9μm厚の銅箔を有する全体厚約1.0鱈の絶
縁板(ガラスクロス基材K、エポキシ樹脂を含浸して積
層接着したもの)に、≠0.1■のドリルで孔を形成し
た。次に、過硫酸アンモニウム水溶液で銅箔表面を清浄
化し、その後、水洗した。
Example 1 An insulating plate (glass cloth base material K, impregnated with epoxy resin and laminated and bonded) with a total thickness of about 1.0 mm and having copper foils of about 9 μm thickness on both sides was drilled with a drill of ≠0.1 mm. A hole was formed. Next, the surface of the copper foil was cleaned with an aqueous ammonium persulfate solution, and then washed with water.

次に15チ塩酸水溶液で処理した後、パラジウムコロイ
ド触媒液に浸漬し、銅箔表面及び孔内壁にパラジウムを
付与した。水洗した後、3.6チ塩酸でパラジウムを活
性化し、水洗を行った。次に1下記組成の化学鋼メッキ
液を用い、消費成分の鋼、ホルマリン、水酸化ナトリウ
ムを補給しつつ、超音波攪拌をして発生する水素を抜き
ながら70℃で約20hメツキした。
Next, the copper foil was treated with an aqueous solution of 15% hydrochloric acid, and then immersed in a palladium colloid catalyst solution to apply palladium to the surface of the copper foil and the inner walls of the holes. After washing with water, palladium was activated with 3.6-dihydrochloric acid and washing with water was performed. Next, plating was carried out at 70° C. for about 20 hours using a chemical steel plating solution having the following composition, while replenishing the consumable components of steel, formalin, and sodium hydroxide, and removing generated hydrogen by ultrasonic stirring.

化学鋼メッキ液組成 硫酸銅         10り/l エチレンジアミン四酢酸 35 f/137チホルマリ
ン     3td/を水酸化ナトリウム    pH
12,8(20℃)量り一ε′ジピリジル    35
m1/1ポリエチレングリコール (分子量600)2
0ゴ/を 次に水洗して乾燥した後、耐エツチング用ドライフィル
ムレジストを両面にラミネートし、0.06鵡幅の回路
及び0.08 tagの間隔を有するフィルムを密着さ
せ、高圧水銀灯で回路を焼付けした。その後、現像し、
更に、塩化鉄エツチング液で回路以外の銅を除去した。
Chemical steel plating solution composition Copper sulfate 10 l/l Ethylenediaminetetraacetic acid 35 f/137 thiformin 3 td/ Sodium hydroxide pH
12,8 (20℃) Measure 1 ε' Dipyridyl 35
m1/1 polyethylene glycol (molecular weight 600)2
After washing with water and drying, a dry film resist for etching resistance was laminated on both sides, a circuit with a width of 0.06 mm and a film with an interval of 0.08 tag were adhered, and the circuit was exposed with a high-pressure mercury lamp. was baked. Then, develop
Furthermore, copper other than the circuit was removed using iron chloride etching solution.

次に回路上の耐エツチング用ドライフィルムレジストを
除去して、高密度回路板を得た。
Next, the etching-resistant dry film resist on the circuit was removed to obtain a high-density circuit board.

この回路板を上面上シ観察した結果、第2図の囚に示す
ように、≠0.1霧の導通接続孔が完全にふさがれた0
、06篩幅の回路が、0.08m幅の間隔をおいて完全
に形成されていた。次に、この回路板の導通接続孔部分
を切断し、断面よシ観察し九結果、導通接続孔全体が完
全に銅で充填された状態になっていた。
As a result of observing the top surface of this circuit board, it was found that the conductive connection hole of ≠0.1 was completely blocked, as shown in Figure 2.
, 06 sieve width circuits were completely formed with intervals of 0.08 m width. Next, the circuit board was cut through the conductive connection hole, and the cross section was observed.As a result, the entire conduction connection hole was completely filled with copper.

実施例2 両面に約18μm厚の銅箔を有する全体厚約0.14−
の絶縁板(ガラスクロス基材にポリイミド樹脂を含浸し
て積層接着したもの)を用い、エキシマレーザ−(波長
308 nm、 パルス出力400mJ、発振時間3Q
nS)で約φ0.05 wmの孔を形成した。以下、実
施例1と同様にして高密度回路板を得た。但し、回路幅
/間隔はO,OS 10、05 tmとした。また、化
学鋼メッキ時間は11hとした。
Example 2 Overall thickness of about 0.14-μm with copper foil about 18 μm thick on both sides
An excimer laser (wavelength 308 nm, pulse output 400 mJ, oscillation time 3Q) was used.
A hole with a diameter of about 0.05 wm was formed using the same method. Thereafter, a high-density circuit board was obtained in the same manner as in Example 1. However, the circuit width/interval was O,OS 10,05 tm. Further, the chemical steel plating time was 11 hours.

この回路板を上面から観察した結果、第2図の■に示す
ように、導通接続孔が完全にふさがれた0、 05 w
m幅の回路が0.05−の間隔で形成されていた。次に
、この回路板の導通接続孔部分を切断し、断面よυ観察
した結果、導通接続孔全体が完全に銅で充填された状態
になっていた。
As a result of observing this circuit board from the top, it was found that the conductive connection hole was completely blocked, as shown by ■ in Figure 2.
m-wide circuits were formed at intervals of 0.05-. Next, we cut the conductive connection hole portion of this circuit board and observed the cross section, which revealed that the entire conduction connection hole was completely filled with copper.

実施例3 実施例2に用いた絶縁板を用い、−0,1mのドリルで
孔を形成した。以下、実施例1と同様にして、表面及び
孔内壁に化学メッキ反応の触媒となるパラジウムを付着
させた。次に前記組成の化学銅メッキ液を用い、表面及
び孔内壁に約1.6μmのメッキ膜を形成した。次に、
水洗した後、5チH,So、で洗浄した後、再び水洗し
た。次に、硫酸銅電気鋼メッキ液(荏原コージライト製
、Cu−BRITE  TH液)を用い、液温30℃、
電流密度λ5A/dm’、空気攪拌と超音波攪拌の併用
で3hめつきを行った。次に、水洗、乾燥した後、実施
例1と同様に、耐エツチング用ドライフィルムレジスト
のラミネート、回路の焼付け、現像、エツチング、耐エ
ツチング用ドライフィルムレジストの除去を行い、高密
度回路板を得た。
Example 3 Using the insulating plate used in Example 2, holes were formed with a -0.1 m drill. Thereafter, in the same manner as in Example 1, palladium, which serves as a catalyst for a chemical plating reaction, was deposited on the surface and the inner wall of the hole. Next, using a chemical copper plating solution having the above composition, a plating film of about 1.6 μm was formed on the surface and the inner wall of the hole. next,
After washing with water, it was washed with 50% H, So, and then washed with water again. Next, using a copper sulfate electric steel plating solution (manufactured by Ebara Cordierite, Cu-BRITE TH solution), the solution temperature was 30°C.
Plating was carried out for 3 hours at a current density of λ5A/dm' and a combination of air stirring and ultrasonic stirring. Next, after washing with water and drying, the dry film resist for etching resistance was laminated, the circuit was baked, developed, etched, and the dry film resist for etching resistance was removed in the same manner as in Example 1 to obtain a high-density circuit board. Ta.

この回路板を上面よシ観察した結果、第2図の(A)I
c示すように、−〇、 1 tmの導通接続孔が完全に
ふさがれた0、06−幅の回路が、0.08m幅の間隔
をおいて形成されていた。次に、この回路板の導通接続
孔部分を切断し、断面よシ観察した結果、導通接続孔全
体が完全に銅で充填された状態になっていた。
As a result of observing this circuit board from the top side, (A) I in Figure 2
As shown in c, 0,06-width circuits in which the -0,1 tm conductive connection holes were completely blocked were formed at intervals of 0.08 m width. Next, the circuit board was cut through the conductive connection hole, and a cross-sectional examination revealed that the entire conduction connection hole was completely filled with copper.

実施例4 厚さ0.75−のベリリアセラミックス(米国プラッシ
ュ・フェルマン社製)KCOsレーザで≠〇、 06 
va、の孔をあけた。次に表面及び孔内壁に化学メッキ
反応の触媒となるPdを付着させ、実施例1と同じ化学
銅メッキにて5hめっきして、厚さ約15μmのメッキ
膜を孔内壁及び表面に析出させた。この状態では孔内は
充填されていないため、体積約4−の銅ボールを札止部
に乗せ、1100℃の電気炉中で約20分間放置してと
シ出した。その結果、銅メッキ膜と銅ボールが溶解して
孔がふさがれた銅張シ状態のセラミック板を得た。この
銅表面を研磨して平担化した後、5tsH,So、で洗
浄し、更に水洗した後で乾燥した。次に耐エツチング用
のドライフィルムレジストをラミネートした。以下、実
施例1と同様にして高密度回路板を得た。
Example 4 0.75-thick beryllia ceramics (manufactured by Plush Ferman, USA) with KCOs laser ≠〇, 06
I made a hole for va. Next, Pd as a catalyst for the chemical plating reaction was attached to the surface and the inner wall of the hole, and plated with the same chemical copper plating as in Example 1 for 5 hours to deposit a plating film with a thickness of about 15 μm on the inner wall and surface of the hole. . In this state, the hole was not filled, so a copper ball with a volume of about 4 cm was placed on the tag part and left in an electric furnace at 1100° C. for about 20 minutes to extrude. As a result, a copper-clad ceramic plate was obtained in which the copper plating film and the copper balls were dissolved and the holes were closed. After polishing the copper surface to make it flat, it was washed with 5tsH, So, further washed with water, and then dried. Next, a dry film resist for etching resistance was laminated. Thereafter, a high-density circuit board was obtained in the same manner as in Example 1.

この回路板を上面より観察した結果、第2図のa3)に
示すように、導通接続孔が完全にふさがれた0、 05
 wg幅の回路がQ、05mの間隔で形成されていた。
As a result of observing this circuit board from the top surface, as shown in a3) of Fig. 2, the conductive connection holes were completely blocked.
Circuits with a width of wg were formed at intervals of Q, 05 m.

次に、この導通接続孔部分を切断し、断面よシ観察した
結果、導通接続孔が完全に銅で充填された状態になって
いた。
Next, this conductive connection hole was cut and the cross section was observed. As a result, the conductive connection hole was completely filled with copper.

本発明の回路板によれば、導通接続孔が回路と一体の同
一金属で充填された構造となっているため、従来のよう
に孔内壁にのみ回路と同一金属で導通化した孔と比較す
ると、スルーホール信頼性が一段と向上する効果をもた
らす。これは、従来法では孔内壁にのみ金属が形成され
て孔食体は空洞になっているのに対し、本発明は金属で
完全に充填されていることの違いKよるものである。こ
の導通接続孔の信頼性を確めるために熱衝撃試験を行な
った結果を第1表に示す。第1表では本発明の実施例1
および2で作成した回路板を比較品と対比した。比較品
は第4図囚に示した従来法の回路板で、これは実施例1
と同じ方法で作成したが、但し、メッキ時間を12hと
し、孔内壁のメッキ膜厚を3011mとしたものである
According to the circuit board of the present invention, the conductive connection hole is filled with the same metal as the circuit, so compared to the conventional hole where only the inner wall of the hole is made conductive with the same metal as the circuit. , which has the effect of further improving through-hole reliability. This is due to the difference that in the conventional method metal is formed only on the inner wall of the hole and the pitting body is hollow, whereas in the present invention the pitting body is completely filled with metal. Table 1 shows the results of a thermal shock test conducted to confirm the reliability of this conductive connection hole. Table 1 shows Example 1 of the present invention.
The circuit board made in 2 and 2 was compared with a comparative product. The comparative product is the conventional circuit board shown in Figure 4, which is the circuit board of Example 1.
It was made using the same method as above, except that the plating time was 12 hours and the thickness of the plating film on the inner wall of the hole was 3011 m.

熱衝撃試験■では、試料を一65℃に2h保ち次に急に
+125℃にして2h保つことを1サイクルとした。熱
衝撃試験■では、288℃の半田に10秒浸けて室温に
冷すことを1回とした。第1表中のデータは分母が観察
スルーホール数で、分子はクラック発生スルーホール数
である。本発明の回路板のスルホール信頼性が優れてい
ることがわかる。
In the thermal shock test (2), one cycle consisted of keeping the sample at -65°C for 2 hours, then suddenly raising it to +125°C and keeping it for 2 hours. In the thermal shock test (2), the sample was immersed in solder at 288° C. for 10 seconds and cooled to room temperature once. In the data in Table 1, the denominator is the number of observed through holes, and the numerator is the number of cracked through holes. It can be seen that the circuit board of the present invention has excellent through-hole reliability.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、導通接続孔を回路と一体の且つ回路と
同一の金属で完全に充填することによシ、部品固定用の
ランドを引き出す必要なしに該導通孔上に直接部品を固
定でき、また該導通孔が導電性ペーストやペレットで充
填されているものではないため、≠0.1 mg以下の
小径孔も可能であシ、孔と孔との間隔が一層狭められる
。従って微細回路の高密度化及び高密反部品実装の両方
が可能となる。
According to the present invention, by completely filling the conduction connection hole with the same metal as the circuit, it is possible to directly fix the component onto the conduction hole without having to pull out a land for fixing the component. Moreover, since the conductive holes are not filled with conductive paste or pellets, small diameter holes of ≠0.1 mg or less are also possible, and the distance between the holes can be further narrowed. Therefore, both high-density microcircuits and high-density anti-component mounting are possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(2)、(3)は本発明の実施例になる回路板の
導通接続孔部分の断面図、第2図囚〜■は本発明実施例
の回路板の導通接続孔部分の回路の平面図、第3図は本
発明実施例の回路板の部品搭載例を示す断面図、第4図
囚〜(ωは従来の回路板の導通接続孔の断面図、第5図
囚、 IB)は従来の回路板の部品搭載例を示す断面図
である。 1・・・絶縁板     2・・・回路3・・・導通接
続孔   4・・・部品の一部5・・・接続バンプ。 第1図 第2図 (A)  (8)   (C)  (D)  (E)第
3図
Figures 1 (2) and (3) are cross-sectional views of the conductive connection hole portion of a circuit board according to an embodiment of the present invention, and Figures 2 (5) to (3) are circuits of the conduction connection hole portion of a circuit board according to an embodiment of the present invention. 3 is a sectional view showing an example of mounting components on a circuit board according to an embodiment of the present invention, FIGS. ) is a sectional view showing an example of mounting components on a conventional circuit board. 1... Insulating plate 2... Circuit 3... Continuity connection hole 4... Part of part 5... Connection bump. Figure 1 Figure 2 (A) (8) (C) (D) (E) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1 表裏回路間、内層回路間、又は表裏回路と内層回路
との間の導通接続孔の全体が、これら回路の金属と一体
で且つそれと同一の金属で完全に充填されていることを
特徴とする回路板。
1. The entire conductive connection hole between the front and back circuits, between the inner layer circuit, or between the front and back circuits and the inner layer circuit is completely filled with the same metal as the metal of these circuits. circuit board.
JP62009542A 1987-01-19 1987-01-19 Circuit board Expired - Lifetime JPH0724334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62009542A JPH0724334B2 (en) 1987-01-19 1987-01-19 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62009542A JPH0724334B2 (en) 1987-01-19 1987-01-19 Circuit board

Publications (2)

Publication Number Publication Date
JPS63177586A true JPS63177586A (en) 1988-07-21
JPH0724334B2 JPH0724334B2 (en) 1995-03-15

Family

ID=11723157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62009542A Expired - Lifetime JPH0724334B2 (en) 1987-01-19 1987-01-19 Circuit board

Country Status (1)

Country Link
JP (1) JPH0724334B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133988A (en) * 1988-11-15 1990-05-23 Shindo Denshi Kogyo Kk Formation of through hole of both-side plastic film circuit board
JPH04188689A (en) * 1990-11-19 1992-07-07 Toshiba Corp Printed wiring board
JPH04209555A (en) * 1989-12-21 1992-07-30 Bull Sa Method for interconnection of metal layers in multilayer network of electronic board and electronic board
JPH07501910A (en) * 1992-09-24 1995-02-23 ヒューズ・エアクラフト・カンパニー Multilayer three-dimensional structure with internal ferromagnetic vias
US6761814B2 (en) 2001-12-20 2004-07-13 Shipley Company, L.L.C. Via filling method
JP2012080002A (en) * 2010-10-05 2012-04-19 Kiyokawa Mekki Kogyo Kk Manufacturing method of wiring substrate
CN108713351A (en) * 2016-03-11 2018-10-26 本田技研工业株式会社 Electronic circuit board and ultrasonic connection method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50111576A (en) * 1974-02-15 1975-09-02
JPS5586198A (en) * 1978-12-23 1980-06-28 Sony Corp Circuit board and method of fabricating same
JPS5883172U (en) * 1981-11-30 1983-06-06 京セラ株式会社 multilayer wiring board
JPS5899856U (en) * 1981-12-28 1983-07-07 松下電工株式会社 electrical circuit board
JPS6076068U (en) * 1983-10-31 1985-05-28 ヤマハ株式会社 printed wiring board
JPS6122693A (en) * 1984-07-10 1986-01-31 日本電気株式会社 Multilayer circuit board and method of producing same
JPS6270467U (en) * 1985-10-23 1987-05-02

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50111576A (en) * 1974-02-15 1975-09-02
JPS5586198A (en) * 1978-12-23 1980-06-28 Sony Corp Circuit board and method of fabricating same
JPS5883172U (en) * 1981-11-30 1983-06-06 京セラ株式会社 multilayer wiring board
JPS5899856U (en) * 1981-12-28 1983-07-07 松下電工株式会社 electrical circuit board
JPS6076068U (en) * 1983-10-31 1985-05-28 ヤマハ株式会社 printed wiring board
JPS6122693A (en) * 1984-07-10 1986-01-31 日本電気株式会社 Multilayer circuit board and method of producing same
JPS6270467U (en) * 1985-10-23 1987-05-02

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133988A (en) * 1988-11-15 1990-05-23 Shindo Denshi Kogyo Kk Formation of through hole of both-side plastic film circuit board
JPH04209555A (en) * 1989-12-21 1992-07-30 Bull Sa Method for interconnection of metal layers in multilayer network of electronic board and electronic board
JPH04188689A (en) * 1990-11-19 1992-07-07 Toshiba Corp Printed wiring board
JPH07501910A (en) * 1992-09-24 1995-02-23 ヒューズ・エアクラフト・カンパニー Multilayer three-dimensional structure with internal ferromagnetic vias
US6761814B2 (en) 2001-12-20 2004-07-13 Shipley Company, L.L.C. Via filling method
JP2012080002A (en) * 2010-10-05 2012-04-19 Kiyokawa Mekki Kogyo Kk Manufacturing method of wiring substrate
CN108713351A (en) * 2016-03-11 2018-10-26 本田技研工业株式会社 Electronic circuit board and ultrasonic connection method
JPWO2017154643A1 (en) * 2016-03-11 2018-11-29 本田技研工業株式会社 Electronic circuit board and ultrasonic bonding method

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