JPS63177468A - Thyristor - Google Patents
ThyristorInfo
- Publication number
- JPS63177468A JPS63177468A JP29908187A JP29908187A JPS63177468A JP S63177468 A JPS63177468 A JP S63177468A JP 29908187 A JP29908187 A JP 29908187A JP 29908187 A JP29908187 A JP 29908187A JP S63177468 A JPS63177468 A JP S63177468A
- Authority
- JP
- Japan
- Prior art keywords
- region
- junction
- biased
- electrode
- thyristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 20
- 239000010410 layer Substances 0.000 description 17
- 239000010408 film Substances 0.000 description 14
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910004077 HF-HNO3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はサイリスタの構造に係シ、特に高信頼性、高耐
圧のサイリスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a thyristor, and particularly to a highly reliable and high voltage thyristor.
単方向性サイリスタもしくは双方向性サイリスタ(トラ
イアック)は、PN接合を複数筒布し、装置動作時、順
方向にバイアスされるPN接合と。A unidirectional thyristor or bidirectional thyristor (TRIAC) consists of multiple PN junctions, and the PN junction is biased in the forward direction during device operation.
逆方向にバイアスされるPN接合を隣接して設ける場合
が多い。その場合、二つの接合にはさまれた層は、しば
しば低濃度にされる。例えば三重拡散製法のサイリスタ
、トライアックで高耐圧分野で使用されるものはその不
純物濃度は極めて低いものとされる。その状態では単な
るPN接合の不安定性(イオン的汚染、結晶欠陥に起因
する)とは別の種類の第1図に示すような不安定性(リ
−理と呼ぶ)において起こシ易い。同図において特性A
は初期の状態、特性BはBT処理後の状態を示す。それ
は、BT処理により、逆バイアス接合側で絶縁膜中、も
しくは絶縁−表面において電荷の分布に変化が生じ、そ
の影響が半導体表面に及び逆バイアス接合の表面空乏層
が異常に伸長して、隣接する頭バイアス接合近傍まで到
着することにより表面リーク電流が生じるものである。Adjacent PN junctions that are biased in the opposite direction are often provided. In that case, the layer sandwiched between the two junctions is often diluted. For example, triple diffusion manufactured thyristors and triacs used in high voltage fields are said to have extremely low impurity concentrations. In this state, a type of instability (referred to as Lie theory), which is different from simple PN junction instability (due to ionic contamination or crystal defects) as shown in FIG. 1, is likely to occur. In the same figure, characteristic A
Characteristic B shows the initial state, and characteristic B shows the state after BT processing. This is because the BT process causes a change in the charge distribution in the insulating film or on the insulating surface on the reverse bias junction side, which affects the semiconductor surface and abnormally extends the surface depletion layer of the reverse bias junction, causing the adjacent Surface leakage current is generated when the current reaches the vicinity of the head bias junction.
該現象は半導体装置を高耐圧化するため、阻止PN接合
の低不純物濃度側の不純物濃度を低くし、表面゛を被覆
する絶縁膜の種類、形成方法、処理プロセスを表面空乏
層がよく伸長するものを選べば選ぶ程、顕著に発生する
ことは明らかである。In order to increase the breakdown voltage of semiconductor devices, this phenomenon lowers the impurity concentration on the low impurity concentration side of the blocking PN junction, and changes the type, formation method, and treatment process of the insulating film that covers the surface so that the surface depletion layer can expand well. It is clear that the more you choose, the more this will occur.
本発明の目的はかかる従来技術による欠点を除去した有
効なサイリスタを提供することである。The object of the present invention is to provide an effective thyristor which eliminates the disadvantages of the prior art.
本発明の特徴は順方向にバイアスされるPN接合と逆方
向にバイアスされるPN接合とを基板表面に有するサイ
リスタにおいて、順方向にバイアスされるPN接合上に
第10電界電極を設は逆方向にバイアスされるPN接合
上に第20電界1!体を設けたことである。The feature of the present invention is that in a thyristor having a forward biased PN junction and a reversely biased PN junction on the substrate surface, the tenth electric field electrode is provided on the forward biased PN junction, and The 20th electric field on the PN junction biased to 1! This is because a body was established.
第20電界電極によυ表面空乏層を伸びやすくしかつ第
10電界電極によりその伸び過ぎを阻止して表面リーク
電流の発生を防止できるから、動作の安定なサイリスタ
が実現できる。Since the 20th electric field electrode makes it easier to extend the υ surface depletion layer, and the 10th electric field electrode prevents it from elongating too much, thereby preventing the generation of surface leakage current, a thyristor with stable operation can be realized.
第2図は本発明による構造と、従来構造のBT処理にお
ける変動状態を下記に述べるプレーナ形サイリスタの場
合について比較したデータで、本発明による構造が十分
に目的を達していることが分かる。同図において特性X
は従従技術によるもので、特性Yは本発明によるもので
ある。FIG. 2 shows data comparing the structure according to the present invention and the fluctuation state in BT processing of the conventional structure in the case of a planar thyristor described below, and it can be seen that the structure according to the present invention fully achieves the purpose. In the same figure, the characteristic
is based on the prior art, and characteristic Y is based on the present invention.
以下図面に基ずいて本発明を説明する。第3図は本発明
の詳細な説明したもので、N型基板1にP型領域2,3
、Pi領域2の内にN+領域9を設け、さらにN中領域
3には空乏層4を伸長させるための従来から用いられて
いる電界電極5が、又P凰領域3には、本発明による、
空乏層4を阻止する電界電極6がそれぞれ設けられてい
る。同図から明らかqように本発明によれば伸長した空
乏層4は電界!、[6により端部7で阻止されるからり
一り電流が少ない安定なものとなる。The present invention will be explained below based on the drawings. FIG. 3 is a detailed explanation of the present invention.
, an N+ region 9 is provided in the Pi region 2, an electric field electrode 5 conventionally used for extending the depletion layer 4 is provided in the N medium region 3, and an electric field electrode 5 according to the present invention is provided in the P region 3. ,
An electric field electrode 6 for blocking the depletion layer 4 is provided respectively. As is clear from the figure, according to the present invention, the elongated depletion layer 4 is exposed to an electric field! , [6, the current is blocked at the end 7, so the current is much smaller and stable.
次に第4図に基すいて本発明の一実施例を説明する。先
ず、N型の半導体基板11に両側から選択的に基板とは
逆電溝形であるP型の不純物を基板を選択的に突き抜け
るまで熱拡散し、拡散層12を形成する。基板と逆電溝
形の不純物を同様に基板に選択的に拡散し、拡散層13
m、13bを形成する。さらに層13!Lの中へ基板と
同電導形であるN型の不純物を選択的に拡散し1層19
を形成する。さらに基板110表面には、拡散中もしく
は、その後で数千λ〜数μの膜厚の絶縁膜18が形成さ
れるが、高耐圧半導体装置の場合、基板の不純物濃度は
、10− のオーダ、場合によりては10 帰 のオー
ダまで低められ、かつ、空乏層14先端の曲率半径を犬
きくして電界集中を緩和するため、絶縁膜18は、上述
したように基板110中の少数キャリアを表面に蓄積さ
せるような種類、作成条件、処理条件が耐圧分布をよく
するために選ばれる。例えば(1)鉛系あるいは亜鉛系
のガラス、あ−る砂は(ii)810□膜とkt203
等金属酸化−へ二
物薄膜を積層した膜、あるいは(iii) s i o
2膜中の正の可動イオンをリンで固定化した後、適当な
表面処理を施こした膜、あるいは、半導体表面を過酸化
水素あるいは過酸化水素にアミン基を含む液を混合した
液で前処理した後、化学反応により低温で被覆した膜等
である。次に従来ニジ用いられている電界電極15およ
び本発明の表面リーク電流の発生を防止する半導体の電
界電極16を形成する。Next, an embodiment of the present invention will be explained based on FIG. First, a diffusion layer 12 is formed by selectively thermally diffusing a P-type impurity having an electric groove shape opposite to that of the substrate from both sides of an N-type semiconductor substrate 11 until it selectively penetrates the substrate. Similarly, impurities in the shape of an electric groove opposite to the substrate are selectively diffused into the substrate to form a diffusion layer 13.
m, forming 13b. 13 more layers! N-type impurities, which have the same conductivity type as the substrate, are selectively diffused into L to form one layer 19
form. Further, on the surface of the substrate 110, an insulating film 18 having a thickness of several thousand λ to several μ is formed during or after the diffusion, but in the case of a high voltage semiconductor device, the impurity concentration of the substrate is on the order of 10 − In some cases, the electric field concentration may be reduced to the order of 10 Ω, and in order to increase the radius of curvature at the tip of the depletion layer 14 to alleviate electric field concentration, the insulating film 18 transfers minority carriers in the substrate 110 to the surface as described above. The type, production conditions, and processing conditions that allow accumulation are selected in order to improve the withstand pressure distribution. For example, (1) lead-based or zinc-based glass, some sand (ii) 810□ membrane and kt203
A film in which thin films of equal metal oxides and two materials are laminated, or (iii) sio
2 After fixing the positive mobile ions in the membrane with phosphorus, the membrane is treated with an appropriate surface treatment, or the semiconductor surface is pretreated with hydrogen peroxide or a mixture of hydrogen peroxide and a liquid containing an amine group. After treatment, it is a film that is coated at a low temperature by a chemical reaction. Next, a conventionally used electric field electrode 15 and a semiconductor electric field electrode 16 for preventing the generation of surface leakage current according to the present invention are formed.
それは先ず絶M膜18に所定のコンタクト用の穴を開け
た後、エピタキシャル技術によりネ細物を含んだ数千え
〜数μの厚さの多結晶シリコン膜を形成し、電界電極1
5.16に相当する部分をフォトレジスト膜で被覆保護
して、HF −HNO3系エツチング液で不要部分を除
去することにより実現される。次にAt、あるいはMo
等単層金属あるいは、Pt−Ti−Au等多層金属によ
りミ極21を形成した後、CV′D技術により低温でS
tO□膜もしくはPSG膜20を形成し、ワイヤゲンデ
ィング部分に所定の穴を開け、裏面にAu蒸着膜により
、オーミックコンタクトのためへ電極を形成し完成する
。First, a predetermined contact hole is made in the absolute M film 18, and then a polycrystalline silicon film with a thickness of several thousand to several micrometers containing nanoparticles is formed using epitaxial technology.
This is achieved by covering and protecting the portion corresponding to 5.16 with a photoresist film and removing the unnecessary portion with an HF-HNO3 etching solution. Next, At or Mo
After forming the myopole 21 with a single layer metal such as Pt-Ti-Au or a multilayer metal such as Pt-Ti-Au, S is heated at low temperature using CV'D technology.
A tO□ film or a PSG film 20 is formed, a predetermined hole is made in the wire ending portion, and an electrode is formed for ohmic contact using an Au vapor-deposited film on the back surface to complete the process.
このようなPNPN構造の半導体装置すなわちす。This is a semiconductor device having such a PNPN structure.
イリスタは、基板110不純物濃度が最も低いため図の
ように電極22に正、電極21に負を印加すると空乏層
14は電界電極15により伸長が促進され領域12へ到
達してしまうか、リーク電流が大となシネ安定となるが
、本発明では電界電極16が設けられているから表面空
乏層が端部17にて阻止され、リーク電流は小となシ安
定なものとなる。In the iristor, since the impurity concentration of the substrate 110 is the lowest, when a positive voltage is applied to the electrode 22 and a negative voltage is applied to the electrode 21 as shown in the figure, the depletion layer 14 is promoted to expand by the electric field electrode 15 and reaches the region 12, or leakage current However, in the present invention, since the electric field electrode 16 is provided, the surface depletion layer is blocked at the end portion 17, and the leakage current becomes small and stable.
ここで電界電極16について、さらに説明を補足するな
らば、その形状は順方向バイアスのPN接合を取シ囲む
ものであれば、例えば丸形リングであっても、角形リン
グでありてもよいことは勿論である。また上記実施例に
て示したようK、半導体装置にかけられるバイアスの極
性が反転することがある場合には両方のPN接合に電界
電極16を形成する方がより有効である。さらにまた電
界電極16は金属で形成することも可能である。しかし
、多結晶シリコン等半導体による電界電極の方が、耐圧
分布の低下を防ぎ、ウェハース当シのペレット収率の低
下を防ぐので、より有利である。To further explain the electric field electrode 16, its shape may be, for example, a round ring or a square ring, as long as it surrounds a forward bias PN junction. Of course. Further, as shown in the above embodiment, if the polarity of the bias applied to the semiconductor device is sometimes reversed, it is more effective to form the electric field electrodes 16 at both PN junctions. Furthermore, the electric field electrode 16 can also be made of metal. However, an electric field electrode made of a semiconductor such as polycrystalline silicon is more advantageous because it prevents a decrease in breakdown voltage distribution and prevents a decrease in pellet yield per wafer.
第5図はラテラル形サイリスタに本発明を適用した第2
0実施例である。第4図と同じ機能の所は同一の符号で
示しであるが、空乏層14の一方の端部17は多結晶シ
リコン半導体の電界電極16によって伸長が阻止される
と同時に他方の端部17′はN+領域23によりて阻止
出来る。Figure 5 shows a second example in which the present invention is applied to a lateral type thyristor.
This is an example. 4 have the same functions as those in FIG. 4, but one end 17 of the depletion layer 14 is prevented from elongating by an electric field electrode 16 made of polycrystalline silicon semiconductor, and at the same time the other end 17' can be prevented by the N+ region 23.
第1図は従来技術によるサイリスタにおける逆電圧とリ
ーク電流との関係を初期状態およびBT処理後の状態に
ついて示したグラフである。第2図はサイリスタにおけ
るBT待時間リーク電流との関係を従来技術および本発
明について示したグラフである。第3図は本発明の詳細
な説明する断面図である。第4図および第5図はそれぞ
れ本発明の第10実施例および第20実施例を示す断面
図である。
面図において、1,11はNu半導体基板、2゜3.1
2,13.13m、13bはPi領領域4,14は空乏
層、5,6.15.16は電界電極、7.7’は空乏層
の端部、8.18は絶縁膜、9,19゜23はN+領領
域20はPSG膜、21,22.24は電極である。
第3図
10° 101102103
逆電圧(V)
87時間(Hr)FIG. 1 is a graph showing the relationship between reverse voltage and leakage current in a thyristor according to the prior art in an initial state and a state after BT processing. FIG. 2 is a graph showing the relationship between the BT waiting time and leakage current in a thyristor for the prior art and the present invention. FIG. 3 is a cross-sectional view illustrating the present invention in detail. FIG. 4 and FIG. 5 are cross-sectional views showing a tenth embodiment and a twentieth embodiment of the present invention, respectively. In the plan view, 1 and 11 are Nu semiconductor substrates, 2°3.1
2, 13.13m, 13b are Pi regions 4, 14 are depletion layers, 5, 6.15.16 are electric field electrodes, 7.7' are the ends of the depletion layers, 8.18 are insulating films, 9, 19 23, the N+ region 20 is a PSG film, and 21, 22, and 24 are electrodes. Figure 3 10° 101102103 Reverse voltage (V) 87 hours (Hr)
Claims (1)
隣接する逆導電型の第2の領域および第3の領域と、該
第20領域内に形成された前記一導電型の第40領域と
を有し、前記第1の領域の不純物濃度は前記第20領域
の不純物濃度より低濃度でありかつ前記第1の領域と前
記第2の領域とで形成されるPN接合は逆方向にバイア
スされており、さらに前記第1の領域と前記第30領域
とで形成されるPN接合は順方向にバイアスされている
サイリスタにおいて、前記第3の領域に接続された第1
の電極が絶縁膜を介して前記第1の領域上に延びるより
に設けられかつ前記第4の領域に接続された第2の電極
が絶縁膜を介して前記第10領域上にまで延びるように
設けられ、前記逆方向にバイアスされているPN接合に
よって前記第1の領域内に拡大する空乏層を前記第2の
電極によって延びやすくし、かつ該空乏層が前記順方向
にバイアスされているPN接合へ到着するのを前記第1
の電極によって阻止していることを特徴とするサイリス
タ。A semiconductor substrate includes a first region of one conductivity type, a second region and a third region of the opposite conductivity type adjacent to the tenth region, and a first region of the one conductivity type formed in the twentieth region. 40 regions, the impurity concentration of the first region is lower than the impurity concentration of the 20th region, and the PN junction formed by the first region and the second region is in opposite directions. In the thyristor, the PN junction formed by the first region and the 30th region is biased in the forward direction.
The electrode is provided so as to extend over the first region through an insulating film, and the second electrode connected to the fourth region extends over the tenth region through an insulating film. A PN junction provided and biased in the forward direction facilitates extension of a depletion layer expanding into the first region by the second electrode, and the depletion layer is biased in the forward direction. said first to arrive at the junction.
A thyristor characterized in that the thyristor is blocked by an electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29908187A JPS63177468A (en) | 1987-11-27 | 1987-11-27 | Thyristor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29908187A JPS63177468A (en) | 1987-11-27 | 1987-11-27 | Thyristor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7855277A Division JPS5412682A (en) | 1977-06-30 | 1977-06-30 | Thyristor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63177468A true JPS63177468A (en) | 1988-07-21 |
Family
ID=17867937
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29908187A Pending JPS63177468A (en) | 1987-11-27 | 1987-11-27 | Thyristor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63177468A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50782A (en) * | 1973-05-02 | 1975-01-07 | ||
JPS5027485A (en) * | 1973-07-11 | 1975-03-20 | ||
JPS52104075A (en) * | 1976-02-27 | 1977-09-01 | Toshiba Corp | Semiconductor element |
JPS538575A (en) * | 1976-07-12 | 1978-01-26 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-11-27 JP JP29908187A patent/JPS63177468A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50782A (en) * | 1973-05-02 | 1975-01-07 | ||
JPS5027485A (en) * | 1973-07-11 | 1975-03-20 | ||
JPS52104075A (en) * | 1976-02-27 | 1977-09-01 | Toshiba Corp | Semiconductor element |
JPS538575A (en) * | 1976-07-12 | 1978-01-26 | Mitsubishi Electric Corp | Semiconductor device |
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