JPS63175779A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To take a diagnosis by using only some of terminals of an LSI by switching current paths between a reference transistor(TR) and a secondary input TR connected thereto on a common emitter basis. CONSTITUTION:Only when input signals Vin1-Vin3 are at L level while a TR Q2 for input control is off, a NOR output and an OR output are obtained which hold a node n1 at H level and a node n2 at L level. When the TR Q2 is turned on, the reference TR Q2 enters a cutoff state regardless of the levels of the signals Vin1-Vin3. Therefore, when a signal lower than a reference voltage VBB2 is applied to the base of a secondary TR Q4 at this time, a current flows from a resistance RC1 through the TRs Q2 and Q3. Further, when a signal higher than VBB2 is applied to the base of the TR Q4, the current flows to the current source CC through the TR Q4. Consequently, when the TR Q2 is on, signals which are in phase with and inverse to an input signal S1 are outputted to nodes n1 and n2 according to the input signal S1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic integrated circuit technology and to technology that is particularly effective when applied to input circuits of bipolar logic integrated circuits.
For example, the present invention relates to a technique that is effective when used as a test signal input method in a logic integrated circuit equipped with a scan type diagnostic circuit.

[Prior Art] In recent years, the number of input/output pins in logic LSIs has increased, and some have as many as 200 to 300 pins. As described above, in a logic LSI with many input/output pins, it becomes difficult to diagnose the internal circuit.

For example, when testing an LSI using a probe inspection, if there are a large number of input/output terminals, the spacing between the terminals becomes narrow, making it extremely difficult to accurately contact all the terminals (pads) with the probe. Especially CCB (controlled collapse bonding)
This becomes difficult in LSIs using the t bonding method.

As a diagnostic method for logic LSIs, a scan method has been proposed that facilitates testing by connecting all flip-flops in a circuit in series and operating them as a shift register (published by Nikkei McGraw-Hill, Inc.).
"Nikkei Electronics 4, April 16, 1979 issue, pp. 57-79).

[Problems to be Solved by the Invention] In the conventional scan-based diagnosis method, it is necessary to design wiring that connects all flip-flops in an LSI in series. Therefore, there is a problem that the number of design steps increases. Also, according to the scan method diagnosis, it is easy to test the logic circuits after the flip-flop, but to check the functionality of the logic gates from the input circuit to the first flip-flop, it is necessary to separately apply a probe to the input pin. It is necessary to input a test signal, which results in the inconvenience that probe testing becomes difficult for LSIs with high terminal density.

An object of the present invention is to enable diagnosis by inputting test signals from all input circuits to internal circuits using only some of the terminals without applying probes to all terminals of the LSI.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a flip-flop is provided corresponding to each input pin, and these are connected in series to form a shift register.The input circuit is also formed from an ECL (emitter cut logic) circuit, and the constant current of the ECL circuit is A second reference transistor is connected between the source and the common emitter terminal of the input transistor, a secondary input transistor whose emitters are commonly connected is provided in parallel with the reference transistor, and the collector terminal of the secondary input transistor is connected between the source and the common emitter terminal of the input transistor. is EC
It is connected to the collector terminal of the first reference transistor of the L circuit, and supplies the data held in the corresponding flip-flop to the control terminal of the secondary input transistor.

[Operation] According to the above-described means, a control signal is input to one of the plurality of input transistors whose emitters are commonly connected to the first reference transistor to stop switching of the current path by the input signal, and instead, By switching the current path between the second reference transistor and the secondary input transistor whose emitters are commonly connected to the second reference transistor, the L
It is possible to achieve the above-mentioned objective of making diagnosis possible by inputting test signals from all input circuits to internal circuits using only some of the terminals without applying probes to all terminals of the SI.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to an ECL type input circuit.

In this embodiment, three input transistors Q, , Q
Yo2jQ1! An input control transistor Q2 is connected in parallel with the input control transistor Q2.

Further, a second reference transistor Q is connected between the common emitter terminal of the transistors Qi1 to Q, , Q, Q2 and the constant current source CC, and the base of this reference transistor Q3 is , reference voltage VBB are applied. Furthermore, in series with the second reference transistor Q1,
The emitters of a secondary input transistor Q4 are commonly connected, and the collector terminal of the secondary input transistor Q4 is connected to the collector terminal of the reference transistor Q1.

An input control signal D1 is applied to the base of the input control transistor Q2, and normally, when the control signal D1 is set to a low level, the transistor Q2 is cut off. .

When this transistor Q2 is turned off, the first
The circuit shown in the figure performs the same logical operation as a normal ECL circuit on the condition that a low-level signal is applied to the base of the secondary input transistor Q4 and the transistor Q4 is off, that is, the input signal V i n engineering ~ Vin
3 are all at a low level, a NOR output and an OR output are obtained in which the node n1 is at a high level and the node n2 is at a low level.

On the other hand, when the input control transistor Q2 is turned on by the control signal D1, the input signals Vin1 to Vin
Regardless of the level of , the first reference transistor Q1 is cut off. Therefore, at this time, the reference voltage VaB is applied to the base of the secondary input transistor Q.
When a signal of a lower level than , is applied, Q4 is turned off and Q is turned on, and the resistor Rc turns on the transistor Q,
, Q, a current flows toward the constant current source CC.

Therefore, Van
When a signal with a higher level than , is applied, Q is turned off, Q4 is turned on, and the current flows through the resistor Re.

The current flows from the current through the transistor Q4 toward the constant current source CC. Therefore, when the input control transistor Q2 is turned on, a signal in phase with the signal S1 is applied to the node n8, and a signal of the signal S1 is applied to the node n2, depending on the input signal S at the base of the secondary input transistor Q4. Inverted signal S1
is output.

FIG. 2 shows an equivalent gate circuit representing the input circuit of FIG. 1 using logic symbols.

From FIG. 2, the circuit of the embodiment has the following effects according to the control signal D□:
It is easily understood that the input signals Vin, -Vin3 are prohibited from being input, and instead, the secondary input signal S1 can be input via another input terminal.

Next, FIG. 3 shows an embodiment in which the input circuit configured as described above is used in a logic LSI diagnostic circuit.

In Fig. 3, symbols INF, , INF, ... engineering N
Pn indicates an input circuit provided corresponding to the input terminals IN2 to INn, and each input circuit INP
Each of the transistors i is constituted by an ECL circuit having a secondary input transistor Q4 as shown in FIG. Then, the OR output of each input circuit INP□ to INPn and the NO
Signal lines (not shown) are arranged so that the R outputs are each supplied to the internal logic circuit ILC.

In addition, the input control terminals of each input circuit INF-INPn (
An input control signal D□ supplied from an external control terminal DD is applied to the base terminal of the transistor Q2, and the input state is controlled by the common control signal D.

Furthermore, corresponding to each input terminal IN□ to INn, a flip-flop FF, FF2. ...FFn are provided, and these flip-flops FF, ~FF
n are connected in series to form a shift register. Moreover, the data held in each flip-flop FF~FFn is stored in the corresponding input circuit INF~INPn.
is supplied to the secondary input terminal (base terminal of transistor Q4). Furthermore, the first-stage flip-flop FF1 among the above-mentioned flip-flops is supplied with the signal input to the input terminal IN□, and is transferred one after another in synchronization with the shift clock SC supplied from the outside. There is. SD○ is flip-flop FF,
This is a terminal provided to output the scan data transferred between FFn and FFn to the outside.

In the above logic LSI, when the input control signal RI applied from the external terminal DD is set to a high level, the input circuits INF1 to INPn all receive input signals from the input terminals IN and INn as described above. It is no longer connected and instead operates by receiving signals from the secondary input terminal. Therefore.

Input test data one after another from the input terminal IN□,
Flip-flops FF1 to FFn with shift clock SC
operate the shift. Then, when all the flip-flops have data, the input circuits INF1 to INP
I'll forward it to n.

Then, the test data set in the flip-flops FF, ~FFn is transferred to the internal thick circuit I through the input circuit.
This allows the logic circuit ILC to be input without using all input terminals to input test data.
can be tested.

On the other hand, during normal use, if the external terminal DD is fixed at a low level, the input control transistor Q2 in the input circuits INF-INPn is cut off, and a human input signal can be accepted, so the input terminal IN □〜INn
If more input signal Vin is input, the original logical operation can be performed.

In the above embodiment, only the input terminal side is shown, but a flip-flop is similarly provided for each terminal on the output terminal side, and these are connected in series to form a shift register, so that the output data can be unified. Can be configured to scan out more than one pin.

As explained above, in the above embodiment, a flip-flop is provided corresponding to each input pin, and the flip-flops are connected in series to form a shift register.

The input circuit is composed of an ECL circuit, and a second reference transistor is connected between the constant current source of the EC and L circuits and the common emitter terminal, and a secondary transistor whose emitters are commonly connected is connected in parallel with this reference transistor. An input transistor is provided, and the collector terminal of this secondary input transistor is connected to the collector terminal of the first reference transistor of the ECL circuit, and its control terminal is supplied with the data held in the corresponding flip-flop. A control signal is input to one of the plurality of input transistors whose emitters are commonly connected to the first reference transistor, and the switching of the current path by the input signal is stopped, and instead, the emitter is commonly connected to the second reference transistor. Because the current path can be switched between the connected secondary input transistors, all input circuits can be connected using only some terminals without applying probes to all terminals of the LSI. This has the effect of allowing diagnosis to be performed by inputting a test signal to the internal circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
A circuit as shown in Figure 1 is used as the input circuit, but a normal ECL circuit is used instead of the circuit in Figure 1.
A circuit that performs the same logical operation as the gate circuit shown in FIG. 2 may be configured.

The above explanation will mainly focus on the bipolar logic LS, which is the application field that was the background of the invention made by the present inventor.
Although the invention has been described as applied to I, the present invention is not limited thereto.

It can also be used for logic LSIs consisting of MOSFETs.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, diagnosis can be performed by inputting test signals from all input circuits to internal logic circuits using only some of the terminals without applying probes to all terminals of the logic LSI.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the input circuit of a logic LSI according to the present invention, FIG. 2 is an equivalent gate circuit showing the circuit of FIG. 1 using logic symbols, and 3@ is the circuit diagram of FIG. FIG. 2 is a block diagram showing a configuration example of a diagnostic circuit using an input circuit. Ql...First reference transistor, Q2...Input control transistor, Q,...Second reference transistor, Q,...Secondary input transistor, Q11~
Q1. ...Input transistor, IN engineering ~ I N n
...Input terminal, FF1□~FFn...Flip-flop, SC...Shift clock.

Claims (1)

[Claims] 1. A first reference transistor to which a reference voltage is applied, one or more input transistors whose emitters are commonly connected to this reference transistor, and a common emitter terminal of these transistors. A second reference transistor is connected between the constant current source and the common emitter terminal, and the emitter is commonly connected in parallel with the second reference transistor, and the collector is connected to the constant current source. A logic integrated circuit comprising an input circuit including a secondary input transistor whose terminal is commonly connected to the collector terminal of the first reference transistor. 2. The logic integrated circuit according to claim 1, further comprising an input control transistor connected in parallel with the input transistor. 3. Flip-flops are provided corresponding to the input circuits, and these flip-flops are connected in series to form a shift register, and the data held in each of the flip-flops is transferred to the secondary input. 3. The logic integrated circuit according to claim 2, wherein the logic integrated circuit can be supplied to a control terminal of a transistor.