JPS6317558A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of damage to an active region due to anisotropic dry etching by selectively forming laminated films con sisting of a first insulating film and a second insulating film having etching selectivity to the first insulating film. CONSTITUTION:An N<+> type semiconductor layer 11 is shaped onto a P-type substrate 10, and an N-type epitaxial layer is grown, thus isolating elements. An silicon oxide film 15, an silicon nitride film 16 and an silicon oxide film 17 are grown, a photo-resist film 18 is applied and left selectively, the films 17, 16 and 15 are etched through RIE and the film 18 is removed and a polycrystalline silicon layer 19 is grown, and a photo-resist film 20 is applied. The silicon oxide films 17 are exposed through etchback by anisotropic dry etching, the residual resist film 20 is peeled, and a P-type impurity is implanted to the polycrystalline silicon layer 19. The oxide film 17 is removed and a photo-resist film 21 is shaped, the polycrystalline silicon layer 19 is removed selectively through etching, the upper section of a collector contact region 14 is masked with a photo-resist film 22, etc. in advance, and the P-type impurity is implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] <Industrial Application Fields> The present invention relates to a method of manufacturing a Levibola type semiconductor device mainly suitable for high-speed logic operation or analog operation in a high frequency region.

(Prior art) Bipolar transistors, which are suitable for high-speed logic operation or analog operation in the high frequency range, are manufactured by using device isolation technology such as buried oxide films or trenches, which forms a shallow vertical junction depth. Various measures are being taken, such as reducing the parasitic capacitance between the base and the collector, reducing the parasitic capacitance between the base, the collector, the base, and the emitter by employing fine lithography technology and self-alignment technology, and reducing the base resistance. Performance improvement has been achieved by using .

The invention described in Japanese Patent Publication No. 57-41826 is known as a device employing such means. The transistor of the invention described in this publication has a base lead-out electrode 6 as shown in the cross-sectional view of FIG.
1 is made of polycrystalline silicon, and a base electrode 63 made of metal is connected to this base lead-out electrode 61 at a position away from the base region 62, thereby reducing the area of the base region 62. The aim is to reduce the parasitic capacitance between the two. However, in this case, the distance between the emitter region 64 and the base extraction electrode 61 is not determined in a self-aligned manner, and the base resistance cannot be sufficiently reduced.

Furthermore, the invention described in Japanese Patent Publication No. 60-28146 is known. The transistor according to the invention described in this publication also uses polycrystalline silicon for the base lead-out electrode, forms an oxide film on the side walls of this base lead-out electrode, and connects the emitter in a self-aligned manner with the separation layer made of the oxide film wall. A base lead-out electrode is formed.

Therefore, it is possible to reduce the base resistance. However, in this case, there is a problem with the manufacturing process. That is, the seventh
As shown in the cross-sectional view of the figure, polycrystalline silicon for the base extraction electrode! By performing side etching 73 on the oxide film 72 under the I71 as a mask material, a portion for obtaining ohmic contact between the base lead electrode and the base region to be formed in a subsequent step is formed. Therefore, from the viewpoint of the manufacturing process, it is very difficult to perform the side etching 73 uniformly. i.e. base resistance, base.

There is a problem in that the parasitic capacitance between the collectors, which is an important factor in transistors, is not uniform, resulting in a low manufacturing yield, which is particularly unfavorable for manufacturing large-scale integrated circuits.

Furthermore, the invention described in US Pat. No. 4,234,3626 is known. As shown in the cross-sectional view of FIG. 8, the method for manufacturing a transistor according to this patented invention involves forming a base lead electrode on a single crystal silicon substrate 81 consisting of a P- type layer, an N+ type layer, an N type layer, and a P type layer. A polycrystalline silicon layer 82 and a first insulating film 83 are sequentially deposited.
An opening 84 is formed on the emitter and base active regions, a second insulating film 1985 is grown thereon, and the second insulating film 85 is selectively removed by anisotropic dry etching to form a second insulating film 1985. The film 85 is the first insulation! 183 and the sidewalls of the base extraction electrode polycrystalline silicon layer 82,
The second insulating layer 985 left on this side wall determines the position of the emitter and the polycrystalline silicon layer 82 for forming the base extraction electrode in a self-aligned manner.

Therefore, both are positioned with the minimum dimensions, thereby achieving low base resistance. However, when removing the second insulating film 85 by anisotropic dry etching, the surface of the underlying single-crystal silicon substrate 81 is exposed to a plasma atmosphere of chlorine gas, which causes damage.
This causes an abnormality in the emitter diffusion region formed in the subsequent process. Furthermore, it is difficult to achieve selectivity in anisotropic dry etching between the polycrystalline silicon layer and the emitter diffusion region made of single crystal silicon, and it is difficult to determine the end point of etching. The drawback is that it lacks mass production.

Incidentally, the anisotropic dry etching technique has the advantage of increasing the precision of processing dimensions when manufacturing semiconductor devices. For this reason, anisotropic dry etching technology is an indispensable technology for this type of method.

(Problems to be Solved by the Invention) As described above, with the conventional technology, the active region is damaged by anisotropic dry etching, the manufacturing yield is low, mass productivity is lacking, and base resistance cannot be reduced. There are various drawbacks such as.

This invention was made in consideration of the above circumstances, and its purpose is to prevent damage to the active region caused by anisotropic dry etching and to sufficiently reduce base resistance. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be manufactured with high manufacturing yield and high mass productivity.

[Configuration of the Invention (Means for Solving Problems)] The method for manufacturing a semiconductor device of the present invention includes a first insulating film on a semiconductor substrate of a first conductivity type, and a first insulating film having etching selectivity. selectively forming a laminated film made of a second insulating film, growing a non-single crystal silicon film around and in the vicinity of the laminated film, and removing the non-single crystal silicon film on the laminated film. a step of introducing an impurity of a second conductivity type into the non-single crystal silicon film; a step of removing the second insulating film; and a step of introducing an impurity of a second conductivity type into the substrate through the first insulating film. forming a first diffusion region by thermally oxidizing the non-single crystal silicon film to form a second diffusion region of a second conductivity type in the base below the non-single crystal silicon film; A third layer is placed on the surface of the silicon film.
a step of forming an insulating film, and a step of forming a first insulating film in the first diffusion region.
and forming a conductive type third diffusion region.

(Function) In the method for manufacturing a semiconductor device of the present invention, a laminated film consisting of a first insulating film and a second insulating film having etching selectivity is selectively formed on a semiconductor substrate of a first conductivity type. This lower substrate is used as the base and the region where the emitter active region is to be formed, and this laminated film is left until the anisotropic dry etching process is completed (thereby, the etching atmosphere during anisotropic dry etching This prevents damage to the base and emitter active regions.

In addition, a non-monocrystalline silicon film is grown around and in the vicinity of the laminated film, only the non-single-crystalline silicon film on the laminated film is removed, and impurities of the second conductivity type are introduced into this non-single-crystalline silicon film. After removing the second insulating film and introducing impurities of the second conductivity type into the substrate through the first insulating film to form a first diffusion region, the non-single crystal silicon film is thermally oxidized to form non-single crystal silicon. By forming a second diffusion region of the second conductivity type in the substrate at the bottom of the film and at the same time forming a third insulating film on the surface of the non-monocrystalline silicon film, the non-monocrystalline silicon film for the base extraction electrode and the emitter region The openings are formed in a self-aligned manner.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view sequentially showing the manufacturing steps when the method for manufacturing a semiconductor device according to the present invention is applied to a bipolar type npn transistor.

First, as shown in FIG. 1 (a), an N+ type single crystal silicon semiconductor 11 is placed on a P type single crystal silicon semiconductor substrate 10.
11 is formed. This semiconductor layer 11 is generally called an N+ buried layer, and is formed to reduce collector parasitic resistance. The formation method may be to introduce n-type impurities such as antimony or arsenic into the substrate 10 by a thermal diffusion method, or by using an ion implantation method. Further, this semiconductor layer 11 is selectively formed at a position where an npn transistor will be formed in the future using lithography technology. Next, an N-type epitaxial layer is grown on the substrate 10 and the semiconductor layer 11 to a thickness of about 1 μm to 2 μm, for example, by an epitaxial growth method. Next, element isolation is performed. This element isolation technology includes
There are various techniques such as those using pn junction, those using selective oxidation, those using buried oxidation, and those using trench method, but in the case of this example, an example using buried oxidation is used. explain. That is, buried oxide 1112 is formed at the boundary between the substrate and the epitaxial layer and within the epitaxial layer to isolate the element from other transistors and to isolate the base/emitter region 13 and collector contact region 14.

Note that n-type impurities are selectively introduced into the collector contact region 14 using lithography technology in order to reduce collector parasitic resistance. The impurity may be introduced by thermal diffusion or ion implantation before element isolation, or by thermal diffusion or ion implantation after element isolation. The above process is no different from the manufacturing process of a normal bipolar type npn transistor. Next, the silicon oxide film on the surface is removed by an etching method to expose the surfaces of the base, emitter region 13 and collector contact region 14 made of the epitaxial layer, and then a silicon oxide film 15 is formed on the surface by, for example, a thermal oxidation method. Grow to a certain thickness. The n-type impurity may be introduced into the collector contact region 14 by selective ion implantation using a resist formed by phosphorography as a mask after the silicon oxide film 15 is grown.

Next, as shown in FIG. 1(1)), a silicon nitride film 16 with a thickness of 100% is deposited by low-pressure chemical vapor deposition (low-pressure CVD).
Grow about 0 people. Furthermore, silicon oxide I was deposited on silicon nitride 1116 by low pressure CVO1 or normal pressure CVD.
I! 17 to about 5,000 to 7,000 people. Note that the silicon nitride w11B and silicon oxide 1
CvD when growing 117 is CvD using plasma.
It may be a VD.

Next, as shown in FIG. 1(C), photoresist*i
After coating a, a resist film 18 is selectively left on a portion of the base and emitter regions 13 and all of the collector contact region 14 using lithography technology, and using this as a mask, a gas such as CF4 is applied. The silicon oxide film 17, the silicon nitride 11116, and the silicon oxide film 17 are etched by an anisotropic dry etching method (for example, RIE, ie, reactive ion etching method). 1115 are selectively and sequentially etched.

This etching is continued until the surface of the base and emitter region 13 made of the epitaxial layer is exposed.

Next, as shown in FIG. 1Ld), after removing the photoresist 1118, a polycrystalline silicon layer 19 as a non-single-crystalline silicon layer is grown by about 4,000 to 5,000 layers by low-pressure CVD. Photoresist g120 is applied again. At this time, as shown in the figure, on the base and emitter regions 13 and on the collector contact region 1,
4, the photoresist film 20 is formed thinner than on other parts.

Next, the photoresist g! When resist 1i120 is etched back by anisotropic dry etching using chlorine-based gas, as shown in FIG.
The polycrystalline silicon w119 below the thinned part is quickly etched, and the silicon oxide film 17 is exposed from this part, while polycrystalline silicon [19] selectively remains in other areas.

Next, the remaining resist [I20] is removed by incineration in an oxygen plasma or treated with a sulfuric acid-based aqueous solution, and then, as shown in FIG. 5oKe■, dose amount 2x10”
An n-type impurity such as boron is implanted into the polycrystalline silicon 1i 119 at a concentration of about 1/cm2.

Note that the polycrystalline silicon layer 19 is formed in advance in the step shown in FIG. 1(d).
By adding an n-type impurity as a dopant when growing the polycrystalline silicon layer 19, the n-type impurity may be implanted simultaneously with the growth of the polycrystalline silicon layer 19.

After this, the silicon oxide film 17 is coated with a buffered hydrofluoric acid aqueous solution.
After removing the photoresist film 21, as shown in FIG. Layer 19 is selectively etched away.

Next, as shown in FIG. 1(h), the collector contact region 14 is masked with a photoresist 1122, etc., and then, for example, an accelerating electric field is
N-type impurities such as boron are implanted at 0 KeV and at a dose of approximately ji2x10''/cm2.The impurity ions implanted at this time are base.

Silicon nitride film 16 left on emitter region 13
It passes through the silicon oxide film 15 below and reaches the base and emitter regions 13. As a result, this base,
A P-type internal base region (active base region) 23 is formed within the emitter region 13 .

Next, as shown in FIG. 1(1), after removing the photoresist m22, the polycrystalline silicon WJ19 is thermally oxidized using the silicon nitride film 16 as a mask, and a silicon oxide film 24 is formed on its surface by 2,000 or more people. Grow by about 3,000 people. As shown here, the n-type impurity added in advance to the polycrystalline silicon layer 19 is diffused to form an external base region (P+ base region) 25. At the same time, the internal base region [23, into which ions have been implanted in advance] is driven diffused. Furthermore, at the same time, the silicon nitride film 16
The sidewalls of the polycrystalline silicon layer 19 adjacent to the sidewalls of the polycrystalline silicon layer 19 are also oxidized, thereby forming a separate base lead-out electrode by the polycrystalline silicon layer 19 and separating this base lead-out electrode from the emitter region to be formed in a subsequent step. Separation takes place simultaneously. During this process, the silicon nitride film 16
If the film thickness of the silicon nitride film 16 is too thick, the side walls of the polycrystalline silicon film 119 will not be sufficiently oxidized, resulting in insufficient separation.On the other hand, if the film thickness of the silicon nitride film 16 is too thin, there will be many pinholes in the silicon nitride film 16. When the polycrystalline silicon layer 19 is oxidized, a portion of the silicon nitride 1116 corresponding to the pinhole position, that is, a region where an emitter region is to be formed later, that is, the surface of the internal base region 23 is oxidized. Therefore, it is necessary to set the thickness of the silicon nitride 1916 so that the above-mentioned disadvantages do not occur, and this thickness is preferably in a range of about 800 to 1000, for example.

Next, as shown in FIG. 1(j), the silicon nitride 1116 is removed by an isotropic dry etching method using, for example, a mixed gas plasma of CF4 and 02, and the underlying silicon oxide film is removed. 15 is removed with a buffered hydrofluoric acid aqueous solution. Here, since the silicon oxide 1924 formed on the surface of the polycrystalline silicon layer 19 is 2000 to 3000 thick, the silicon oxide 1924 on the collector contact region 14 and the internal base region 23 [115
The surface of the collector contact region 14 and the internal base region 23 are exposed. In addition,! Since the wet etching method using an aqueous hydrofluoric acid solution is isotropic etching, the silicon that separates the base lead electrode made of the polycrystalline silicon layer 19 from the surface of the internal base region 23 where the emitter region is to be formed is etched. Side etching may occur in the oxide film 24, and the opening width for the emitter region may become large. To prevent this,
The silicon oxide film 15 may be removed by an anisotropic dry etching method using a gas such as CF4. This CF4
Compared to the chlorine-based gas plasma used when etching polycrystalline silicon films, gas plasmas such as Etching etching cause much less damage to single-crystal silicon films, and are more effective at etching silicon oxide films and single-crystal silicon films. It is also possible to obtain sufficient selectivity. Therefore, the etching step for exposing the surface of the internal base region wt23 does not damage the surface, and does not affect the thermal diffusion step performed in the subsequent step.

Next, a polycrystalline silicon layer 26 is grown by low pressure CvD, and n-type impurity ions such as arsenic are added to this polycrystalline silicon 1i26 by ion implantation.

In addition, this polycrystalline silicon! When growing 126,
A film containing an n-type impurity such as arsenic may be grown. Then, using lithography technology, the polycrystalline silicon layer 26 is left only on the collector contact region 14 and the surface of the internal base region 123, and then an n-type impurity is diffused from the polycrystalline silicon layer 26 by thermal oxidation or the like. An emitter region 27 is formed on the surface of the internal base region 23 by performing the following steps.

After this, as shown in FIG. 1(k), using the polycrystalline silicon layer 26 as a mask, a buffered hydrofluoric acid aqueous solution or the like is used to oxidize the silicon on the polycrystalline silicon layer 19 as the base extraction electrode. 124 is selectively removed, and an interlayer insulating film 28 such as a silicon oxide film is grown by CVD.
Next, contact holes 29, 30, and 31 communicating with the surface of the polycrystalline silicon layer 26 and the surface of the polycrystalline silicon layer 19 at the two locations are opened in this interlayer insulating film 28 using lithography technology. Furthermore, a film made of a metal material for wiring, such as aluminum, an alloy of aluminum and silicon, an alloy of aluminum, silicon and copper, etc., is deposited on this, and this is applied to each of the contact holes 29 by lithography. 30.31 leaving only the collector electrode 32. An emitter electrode 33 and a base electrode 34 are formed. Then, the entire surface is covered with a surface protection film (not shown) to complete the npn transistor.

As described above, in the method of the above embodiment, when anisotropic dry etching is performed using chlorine-based gas plasma that damages the single crystal silicon layer, the emitter region 2
Since the silicon nitride film 16 is provided on the active region where 7 is formed, the surface of the active region is not exposed to the plasma atmosphere of anisotropic dry etching. Therefore, the surface is not damaged and the subsequent thermal oxidation process is not affected. Therefore, the dimensions of the transistor can be reduced by utilizing the high dimensional accuracy of the anisotropic dry etching method.

Furthermore, by oxidizing the sidewalls of the polycrystalline silicon layer 19 adjacent to the sidewalls of the silicon nitride film 16, the polycrystalline silicon layer 19 forms a separate base lead-out electrode and separates this base lead-out electrode from the emitter region 27 that will be formed later. Since both are silicon oxide film 2
The separation is achieved with a minimum dimension of 4 mm in thickness and in a self-aligned manner. In addition, since there are no special processes, it is possible to improve manufacturing yields and improve the quality of the building.

Note that this invention is not limited to the above embodiments (
Needless to say, various modifications are possible. For example, in the method of the above embodiment, the silicon oxide film 24 grown on the polycrystalline silicon 1ii19 is removed before the interlayer insulating film 28 is grown. The reason for this is that when forming the contact holes 29, 30, 31 for connecting the collector, emitter, and base electrodes 32, 33, and 34,
This is to keep the thickness of the insulating film constant at each electrode position. If this is not kept constant, side etching will occur in the insulating film at thinner parts, causing problems. However, if etching is performed under conditions that provide good selectivity with the base film in anisotropic dry etching method 1, the contact hole may be opened with the silicon oxide G124 left as it is without removing it. . FIG. 2 is a sectional view showing the final configuration of an npn transistor manufactured through such steps. Note that in FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

Furthermore, in the method of the embodiment shown in FIGS. 1 and 2 above, a case has been described in which element isolation from other elements and isolation between the collector region and the base and emitter regions are performed by buried oxidation. As described above, isolation using a pn junction, isolation using a trench method, etc. can also be used.

FIG. 3 is a cross-sectional view showing a final configuration in which pn junction isolation is used instead of buried oxidation for element isolation. In this method, after forming a highly impurity-concentrated N+ type groove conductor layer 11 on a P type substrate 10, an epitaxial layer 40 is grown thereon.

Next, a P-type diffusion region 41 is formed in this epitaxial layer 40 by thermal diffusion or ion implantation to perform element isolation. Thereafter, an N1 type region 42 for reducing collector parasitic resistance is formed in the epitaxial layer 40 by diffusion to reach the N+ type groove conductor layer 11, and then a silicon oxide film 43 is formed by selective oxidation to form an element. Separation and N-type region 42 base, emitter region (region 23.
25.27). The subsequent steps are similar to those in the embodiment shown in FIG. 1, and parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and their explanation will be omitted.

FIG. 4 is a cross-sectional view showing a final structure obtained by a method in which two types of trenches, a shallow trench and a deep trench, are employed instead of buried oxidation for element isolation. In this method, an N+ type ring conductor layer 51 with an impurity concentration is deposited on a P type substrate 50, an N type epitaxial layer 52 with a low impurity concentration is deposited on this N+ type half layer 51, and then a shallow trench is deposited. Minute! An l region 53 is formed to connect the collector contact region 14 and the base.

The emitter region 13 is separated from the substrate 5.
A deep trench isolation region 54 reaching within 0 is formed to isolate the device from other devices. Furthermore, n-type impurities are introduced into the collector contact region 14 at a high concentration for the purpose of reducing collector parasitic resistance.

The subsequent steps are the same as in the embodiment shown in FIG.
The same reference numerals are given to the parts corresponding to those in the figure, and the explanation thereof will be omitted.

FIG. 5 is a cross-sectional view showing the final structure obtained by employing a deep trench and selective oxidation instead of buried oxidation for element isolation. In this method, a highly impurity-concentrated N++ semiconductor 1
i151, an N-type epitaxial layer 52 with a low impurity concentration is sequentially deposited on this N-type half layer 51, and a deep trench isolation region w<54 is first formed so that the bottom thereof is inside the substrate 50. The device is separated from the other devices. Next, silicon oxide g155 is formed by selective oxidation to separate the collector contact region 14 from the base and emitter regions 13.

The subsequent steps are the same as in the embodiment shown in FIG.
The same reference numerals are given to the parts corresponding to those in the figure, and the explanation thereof will be omitted.

As described above, according to each of the embodiments described above, the dimensions of the transistor can be reduced by utilizing the high dimensional accuracy of the anisotropic dry etching method without damaging the surface of the active region. Furthermore, the formation of the base lead-out electrode and the separation of this base lead-out electrode from the emitter region 27, which will be formed later, are performed using silicon oxidation II! Since this is done by forming the silicon oxide film 24, both of the silicon oxide films 24
The separation is achieved in a self-aligned manner with the minimum film thickness of , making it possible to achieve a significant reduction in base resistance and miniaturization of the device.

In each of the above embodiments, the case where the base lead-out electrode and the like are constituted by the polycrystalline silicon layer 19 has been described, but this is generally called polycide, in which the lower layer is a polycrystalline silicon layer and the upper layer is made of molybdenum, titanium, molybdenum, titanium, molybdenum, titanium, etc. The base lead-out electrode or the like may be configured with a two-layer structure of a compound of a high melting point metal such as tungsten and silicon. Note that a layer made of amorphous silicon can be used as the polycrystalline silicon layer 19 used as the non-single crystal silicon layer.

[Effects of the Invention] As explained above, according to the present invention, it is possible to prevent damage to the active region caused by anisotropic dry etching, and to sufficiently reduce the base resistance. A method for manufacturing a semiconductor device with high manufacturing yield and high mass productivity can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a manufacturing process according to an embodiment of the present invention, FIGS. 2 to 5 are sectional views for explaining other embodiments of the invention, and FIGS. 6 to 8 Each figure is a sectional view of a conventional example. 10... P-type single crystal silicon semiconductor substrate, 11...
- N+ type single crystal silicon semiconductor layer, 12... Buried oxide film, 13... Base, emitter region, 14... Collector contact region, 15.17.24... Silicon oxide film, 16. ...Silicon nitride film, 18.20.2
1.22... Photoresist film, 19.26... Polycrystalline silicon layer, 23... Internal base region (active base region), 25... External base region (P+ base region), 27...・Emitter region, 28... interlayer insulating film,
29.30.31...Contact hole, 32...
Collector electrode, 33... Emitter electrode, 34... Base electrode. Applicant's representative Patent attorney Takehiko Suzue (d) (e) (f) (h) (+) Figure 1 (j) (k) Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Scope of Claims] 1. A step of selectively forming a laminated film consisting of a first insulating film and a second insulating film having etching selectivity on a semiconductor substrate of a first conductivity type; A step of growing a non-monocrystalline silicon film around and in the vicinity of the laminated film, a step of removing the non-single-crystalline silicon film on the laminated film, and introducing a second conductivity type impurity into the non-single-crystalline silicon film. a step of removing the second insulating film; a step of introducing an impurity of a second conductivity type into the substrate through the first insulating film to form a first diffusion region; a step of thermally oxidizing to form a second diffusion region of a second conductivity type in the base under the non-single crystal silicon film and at the same time forming a third insulating film on the surface of the non-single crystal silicon film; A method for manufacturing a semiconductor device, comprising the step of forming a third diffusion region of the first conductivity type within the region. 2. When forming a third insulating film on the surface of the non-single crystal silicon film, the third insulating film is formed on the side wall of the non-single crystal silicon film adjacent to the side wall of the first insulating film and on the upper surface thereof. A method for manufacturing a semiconductor device according to claim 1. 3 The first insulating film has a thickness of 800 Å to 1000 Å.
2. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed so as to fall within the range of . 4. After growing the non-single crystal silicon film, an organic film is formed by coating, and the non-single crystal silicon film on the laminated film is removed by etching back by dry etching to flatten the surface. A method for manufacturing a semiconductor device according to claim 1. 5. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity of a second conductivity type is introduced into the non-single crystal silicon film at the same time as the non-single crystal silicon film is grown. 6. The method of manufacturing a semiconductor device according to claim 1, wherein a layered structure film consisting of a polycrystalline silicon layer and a compound layer of a high melting point metal and silicon is formed in place of the non-monocrystalline silicon film. . 7. Manufacturing the semiconductor device according to claim 1, further comprising the step of removing the first insulating film using the third insulating film as a mask before forming the third diffusion region. Method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of removing the first insulating film is performed by an etching method having etching selectivity with respect to the underlying substrate. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the etching method is an isotropic dry etching method. 10 Selectively forming a first single-crystal silicon semiconductor region of a second conductivity type with a relatively high impurity concentration on a single-crystal silicon substrate of a first conductivity type; a step of forming a second single crystal silicon semiconductor region of a second conductivity type with a relatively low impurity concentration, and a step of separating the second single crystal silicon semiconductor region with an insulating layer to form a base, an emitter region, and a collector contact region. A first laminated film consisting of a first insulating film and a second insulating film having etching selectivity is formed on the entire surface of the collector contact region, and at the same time, the base,
A second insulating film consisting of a first insulating film and a second insulating film having etching selectivity with respect to the first insulating film is formed only at a predetermined position on the emitter region.
selectively forming a laminated film; growing a first non-single crystal silicon film around and in the vicinity of the first and second laminated films; and growing a first non-single crystal silicon film on the first and second laminated films. a step of removing a non-single crystal silicon film; a step of introducing impurities of a first conductivity type into the first non-single crystal silicon film; and a step of removing a second insulating film of the first and second laminated films. selectively removing the first non-single-crystal silicon film at positions other than around and in the vicinity of the second laminated film; By introducing conductivity type impurities to form an internal base region and thermally oxidizing the first non-single crystal silicon film, the first conductivity type is formed from the first non-single crystal silicon film into the base and emitter regions. a step of diffusing impurities to form an external base region, and forming a third insulating film on the surface of the first non-single crystal silicon film to separately form a base extraction electrode in contact with the surface of the external base region; 1st
and removing the first insulating film of the second laminated film to expose the surfaces of the collector contact region and the internal base region; 2
The method includes a step of selectively forming a non-single crystal silicon film, and a step of diffusing impurities of a second conductivity type into the internal base region through the second non-single crystal silicon film to form an emitter region. A method for manufacturing a semiconductor device, characterized in that: 11 When forming a third insulating film on the surface of the first non-single crystal silicon film, a side wall of the first non-single crystal silicon film adjacent to a side wall of the first insulating film of the second stacked film and an upper surface thereof Claim 10: A third insulating film is formed.
A method for manufacturing a semiconductor device according to section 1. 12 The first insulating film has a thickness of 800 Å to 1000 Å.
Claim 10 is formed to have a range of Å.
A method for manufacturing a semiconductor device according to section 1. 13 After growing the first non-single crystal silicon film,
Claim 1, wherein the first non-single crystal silicon film on the first and second laminated films is removed by forming an organic film by coating and flattening the surface by etching back using a dry etching method. The method for manufacturing a semiconductor device according to item 10. 14. Manufacturing a semiconductor device according to claim 10, wherein impurities of a first conductivity type are introduced into the first non-single crystal silicon film at the same time as the first non-single crystal silicon film is grown. Method. 15. Claim 1, wherein a laminated structure film consisting of a polycrystalline silicon layer and a compound layer of a high melting point metal and silicon is formed in place of the first non-single crystal silicon film.
A method for manufacturing a semiconductor device according to item 0. 16. The method of manufacturing a semiconductor device according to claim 10, wherein the first insulating film is removed using the third insulating film as a mask. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of removing the first insulating film is performed by an etching method having etching selectivity with respect to the underlying single crystal silicon semiconductor region. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the etching method is an isotropic dry etching method.