JPS6317481U - - Google Patents
Info
- Publication number
- JPS6317481U JPS6317481U JP10898086U JP10898086U JPS6317481U JP S6317481 U JPS6317481 U JP S6317481U JP 10898086 U JP10898086 U JP 10898086U JP 10898086 U JP10898086 U JP 10898086U JP S6317481 U JPS6317481 U JP S6317481U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output signal
- converter
- output
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図、第３図を説明するための波形
説明図、第３図は従来装置の一実施例を示すブロ
ツク図であり、図において１は可変減衰器、２は
カツプラ、３は検波器、４は誤差増幅器、５はア
ナログサンプルホールド回路、６は減衰器ドライ
バ、７はＡ／Ｄ変換器、８はＤ／Ａ変換器、９は
スイツチである。なお各図中同一符号は同一また
は相当部分を示すものとする。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a waveform explanatory diagram for explaining Figs. 1 and 3, and Fig. 3 is a block diagram showing an embodiment of a conventional device. In the figure, 1 is a variable attenuator, 2 is a coupler, 3 is a detector, 4 is an error amplifier, 5 is an analog sample hold circuit, 6 is an attenuator driver, 7 is an A/D converter, and 8 is a D/A The converter 9 is a switch. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
と、この可変減衰器の出力信号が入力されるカツ
プラと、このカツプラの２つの出力端子の１つと
接続された検波器と、この検波器出力を増幅する
誤差増幅器と、この誤差増幅器の出力信号が入力
されるアナログサンプルホールド回路と、２つの
入力接点をもちその一つの接点がアナログサンプ
ルホールド回路に接続されたスイツチと、このス
イツチの出力接点からの出力信号が入力され、か
つ上記可変減衰器に出力信号を与える可変減衰器
ドライバと、上記誤差増幅器出力信号が入力され
るＡ／Ｄ変換器と、このＡ／Ｄ変換器の出力信号
が入力され、かつその出力信号が上記スイツチの
もう一方の入力接点に接続されるＤ／Ａ変換器と
で構成されたレーダ装置の自動振幅制御回路。 A variable attenuator to which the transmission signal of the radar device is input, a coupler to which the output signal of the variable attenuator is input, a detector connected to one of the two output terminals of the coupler, and a detector that outputs the output of the detector. An error amplifier to amplify, an analog sample hold circuit into which the output signal of this error amplifier is input, a switch having two input contacts, one of which is connected to the analog sample hold circuit, and an output contact of this switch. an A/D converter to which the error amplifier output signal is input, and an A/D converter to which the output signal of the A/D converter is input; and a D/A converter whose output signal is connected to the other input contact of the switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10898086U JPS6317481U (en) | 1986-07-16 | 1986-07-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10898086U JPS6317481U (en) | 1986-07-16 | 1986-07-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6317481U true JPS6317481U (en) | 1988-02-05 |
Family
ID=30986668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10898086U Pending JPS6317481U (en) | 1986-07-16 | 1986-07-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6317481U (en) |
-
1986
- 1986-07-16 JP JP10898086U patent/JPS6317481U/ja active Pending
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