JPS63174351A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To remove the stepping on the surface of a semiconductor substrate by a method wherein the polycrystalline silicon layer, to be used as the electrode on which an information charge storage capacitance will be formed, is buried in the surface of the semiconductor substrate. CONSTITUTION:On a P-type substrate 1, an N<+> diffusion layer 5, a field oxide film 2, tie first layer of polycrystalline silicon layer 3, the second layer of polycrystalline silicon layer 7, the first layer of Al wiring layer 6, the second layer of Al wiring layer 8, an interlayer insulating film 9 and the like are laminated. As said layer 3 is buried in the surface of the substrate 1, the stepping generating between the surface of the substrate 1 and the layer 3 can be removed. A grooving isolation region is formed on the circumference of a memory cell MC, an information charge storage capacitance CP is formed by the layer 3 utilyzing the side face of said isolation region, a capacitor insulating film 4, and an N<+> diffusion layer 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and more specifically,
This invention relates to an improvement in a memory cell structure suitable for high integration in semiconductor memory devices.

[Conventional technology]

As an example of a conventional device configuration of this type, here is a circuit pattern showing a memory cell of a highly integrated dynamic semiconductor memory device proposed in lecture number FAX 17.4 at the International Solid State Circuit Conference (ISSCC85) in 1885. A plan view is shown in FIG. 3, and a sectional view taken along line mV-IV in FIG. 3 is shown in FIG. 4.

In the conventional configurations shown in FIGS. 3 and 4, reference numeral 1 denotes a P-type silicon semiconductor substrate, and on this P-type substrate 1, an N+ diffusion layer 5. A field oxide film 2 separating a plurality of memory cells from each other, a first polycrystalline silicon layer 3a, a second polycrystalline silicon layer 7. First layer Ai wiring layer B
, second layer AJ2° wiring layer 8. A living room insulating film 3 and the like are laminated.

In this case, the first hybridization line layer 6 forms a bit line and is electrically connected to the N+ diffusion layer 5 via the contact hole 10, and The second polycrystalline silicon layer 7 forms a word line, which is short-circuited at regular intervals by the second Al wiring layer 8 to reduce its resistance.

Here, a trench isolation region is formed around memory cell MC to isolate each memory cell, and the side surface of this trench isolation region is used to separate the first layer of polycrystalline. An information charge storage capacitor C2 is formed by the silicon layer 3a, the capacitor insulating film 4 (part of the field oxide film 2), and the N+ diffusion layer 5, and a similar structure is also formed in the flat part of the memory cell MC. An information charge storage capacitor is formed.

Therefore, in this conventional technology, by utilizing the trench isolation region on the outer periphery of C in the memory cell as the information charge storage capacitor C1, the area of the flat part forming the information charge storage capacitor C1 is reduced, that is, the chip area is reduced. Even if the size is reduced, the operating margin is sufficiently wide and the storage capacity can be secured to hold sufficient storage information charge for minority carriers injected by radiation such as α particles.

Furthermore, as is clear from the circuit pattern configuration in Figure 3,
It is obvious that the longer the trench isolation region, that is, the peripheral length of the memory cell MC, is used, the smaller the trench depth required to obtain the same amount of information charge storage capacitance C1 can be made. It can be said that a memory cell MC having a structure in which the grooved isolation region is used both for isolation between each memory cell MC and for a part of the information charge storage capacity is suitable for a highly integrated semiconductor device.

□On the other hand, in order to realize even more highly integrated semiconductor memory devices, multilayer wiring technology is essential, and even in the conventional configuration, the first layer of A Wiring layer 6. The second polycrystalline silicon layer that forms the word line? , and the second layer of An wiring layer 8 to reduce the resistance of the word line.The most important point in such multilayer wiring is that each wiring layer This is a mutual planarization technology, and if there is a large level difference in the wiring base, it is easy to cause disconnection or thinning of each wiring layer, or electrical short circuit between adjacent wiring layers.

[Problem that the invention seeks to solve]

However, in the case of the conventional configuration, information charge storage capacitors C2 and C2 are formed as memory cells MC. The step on the semiconductor substrate 1 caused by the formation of the first polycrystalline silicon layer 3a serving as one electrode corresponds to the step formed on the first Al wiring layer 6. Second layer polycrystalline silicon layer 7. Furthermore, this method has a problem that is not desirable for achieving high integration of the device, in that it impedes planarization of the three-layer wiring of the second-layer An wiring layer 8.

Therefore, an object of the present invention is to effectively utilize multilayer interconnection technology to further increase the performance of a capacitor cell using a grooved isolation region in view of the above-mentioned problems with conventional devices. integrated. An object of the present invention is to provide a semiconductor memory device of this type.

[Means for solving problems]

In order to achieve the above object, a semiconductor memory device according to the present invention includes an information charge storage capacitor C as a memory cell MC.
By embedding the first layer of polycrystalline silicon as one electrode, where electrodes 1 and C9 are formed, into the surface of the semiconductor substrate, the level difference on the semiconductor substrate is eliminated.

[For production]

That is, in this invention, in order to embed the first polycrystalline silicon layer in the semiconductor substrate surface, the first layer of An, which is disposed and formed on the first polycrystalline silicon layer, is
The planarization of the three-layer interconnection layer, the interconnection layer, the second polycrystalline silicon layer, and the second Al interconnection layer, can be significantly improved, making it possible to form multilayer interconnections under even stricter design standards. This makes it possible to realize an even more highly integrated semiconductor memory device.

[Embodiment] Hereinafter, an embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a plan view of a circuit pattern showing a memory cell of a highly integrated dynamic semiconductor memory device to which this embodiment is applied, and FIG. 2 is a sectional view taken along line rl-II of the same. In these FIG. 1 and FIG. 2 embodiments, the above-mentioned FIG. 3,
The same reference numerals as in the conventional example in FIG. 4 indicate the same or corresponding parts,
In this embodiment, the memory cell configuration is the same as that in the conventional example.

That is, also in the embodiment configurations of FIGS. 1 and 2, reference numeral 1 is a P-type silicon semiconductor substrate, and this P
On the type substrate l, an N+ diffusion layer 5. Field oxide film 2.
First layer polycrystalline silicon layer 3. Second layer polycrystalline silicon layer 7. 1st layer Aii line layer 6. Second layer Al wiring layer 8. In this embodiment, the first polycrystalline silicon layer 3a formed on the P-type substrate 1 in the conventional example is replaced with the P-type substrate 1.
By making the first polycrystalline silicon layer 3 buried in the plane, the level difference between the substrate 1 surface and the substrate M3 is eliminated.

Furthermore, even in this case, the Ai of the first layer
The second polycrystalline silicon layer 7 forms a wiring layer line and a bit line, and is electrically connected to the N+ diffusion layer 5 through a contact hole 10. The second layer A is formed at regular intervals.
It is short-circuited by the l wiring layer 8, and its resistance is reduced.

As you can see, a trench isolation region is formed around memory cell MC to isolate each memory cell, and the side surface of this trench region 5uiii is used to separate the first layer of polycrystalline material. An information charge storage capacitor C1 is formed by the silicon layer 3, the capacitor healing film 4 (a part of the field oxide film 4), and the N+ diffusion layer 5, and a similar structure is formed in the flat part of the memory cell. The structure forms an information charge storage capacitor.

In other words, the configuration of this embodiment and the configuration of the conventional example are particularly different from each other in the case of the configuration of this embodiment, as is clear from the comparison between FIGS. 2 and 4.

One conductive layer as a memory electrode, in this case the first layer polycrystalline silicon layer 3a, which was formed on the surface of the P-type substrate in the conventional configuration, is replaced by a conductive layer buried within the surface of the P-type substrate. 1
Since this is the second polycrystalline silicon layer 3, this first
P-type substrate 1 with formation of polycrystalline silicon layer 3
The first-layer Ai wiring M6. which forms the bit line described above is arranged and formed on the first-layer polycrystalline silicon layer 3 without causing a step difference in plane. 7. Second layer of polycrystalline silicon layer forming a word line. Moreover, the three-layer wiring of the second layer Al wiring layer 8, which aims to reduce the resistance of the word line, can be formed with much better flatness when compared with the conventional structure.

In the above embodiments, the present invention is applied to a memory cell of a highly integrated dynamic semiconductor memory device proposed at the International Solid State Circuits Conference WCl55CC85) in 1885, but other trenching methods may also be used. It goes without saying that the present invention can also be applied to memory cells of semiconductor memory devices that employ the separation method, and similar effects and effects can be obtained.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a semiconductor memory device in which an information charge storage capacity of a memory cell is configured on a semiconductor substrate surface including a side surface of a grooved region using one conductive layer as an electrode, an electrode is provided. By embedding a conductive layer in the surface of the semiconductor substrate, the height difference in the substrate surface due to the formation of the conductive layer can be reduced. The first A-crossing line layer forming the bit line, the second polycrystalline silicon layer forming the word line, and the word line are formed on the crystalline silicon layer. The three-layer wiring of the second A-crossing line layer can be formed with much better flatness compared to the conventional structure, and therefore there is no possibility of disconnection or thinning of each layer, or of wires between adjacent layers. It eliminates the risk of electrical short circuits, and also enables the formation of multilayer wiring layers under stricter design standards compared to conventional configurations, resulting in even higher integration. It has excellent features such as being able to realize a semiconductor memory device with a high level of performance.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a circuit pattern showing a memory cell of a highly integrated dynamic semiconductor memory device to which an embodiment of the present invention is applied, FIG. 4 is a plan view of a circuit pattern showing a memory cell of a conventional highly integrated dynamic semiconductor memory device, and FIG. MC...Memory cell, S...Information charge storage capacity in the flat area, C2...Information charge storage capacity in the grooved isolation region. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Field oxide film, 3... First layer polycrystalline silicon layer, 4...
・Capacitor insulating film, 5...N+ diffusion layer, 6...
- First layer AfL wiring layer (bit line), 7... Second layer polycrystalline silicon layer (word line), 8... Second layer A cross line layer, 9... ...Interlayer insulating film, 10...
・Contact hole. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] It has a plurality of memory cells formed on a semiconductor substrate,
The memory cells are separated from each other by an insulating film in the grooved region, and the information charge storage capacity of each memory cell is formed on the semiconductor substrate surface including the side surface of the grooved region using one conductive layer as an electrode. 1. A semiconductor memory device, characterized in that a conductive layer serving as the electrode is buried in the surface of the semiconductor substrate to reduce a level difference in the substrate surface due to the formation of the conductive layer.