JPS63174142A - Task tracking system - Google Patents

Abstract

PURPOSE:To prevent the processing performance of a data processor from being lowered and to compress a memory capacity for accumulating a trace data, by collecting only a data with respect to a specific processing from a data collection function for the operation analysis of the data processor. CONSTITUTION:A module 1i reads out the data in a data area 52b on a shared memory 52 under the control of a microprocessor 31 and a bus control circuit 34. The data is processed according to the data of control information areas 17 in task control blocks 14(0)-14(2) that are control data in a task control block area 52a. At this time, if a trace object display flag 17a on the control data in the area 52a is set at 1, trace information such as a data address and a processed content represented as the trace control word of the area 17 is recorded on the trace data 33 of a control memory 32. A collected trace data is sent to the outside via a module having an external interface.

Description

[Detailed Description of the Invention] [Summary] A task tracing method for a data processing device in which a plurality of functional modules are interconnected via a common bus, which collects data for analyzing the operation of the data processing device. By configuring the trace function to collect only data related to a specific process, a decrease in the processing performance of the data processing device due to data collection (data trace) can be prevented, and the memory for storing trace data can be reduced. It becomes possible to

[Industrial application field]

The present invention relates to a task tracing method for a data processing device in which a plurality of functional modules are interconnected via a common bus.

For example, in order to analyze the internal operation of a data processing device to detect a failure or improve its performance, it is effective to collect and analyze control data within the data processing device along its processing process.

In addition, in the common bus control method, data processing is performed by multiple functional modules independently or in combination with each other.
Tracing and analyzing the data of all these functional modules involves various problems as described below.

In other words, extracting data related to one process from the collected trace data generates overhead for tracing, increases memory to store unnecessary trace data, and requires a data extraction function for analysis. resulting in disadvantages.

For this reason, a method is expected to perform such data tracing efficiently and in a simple manner.

[Conventional technology]

FIG. 3 shows a block diagram illustrating a conventional example.

In FIG. 3, numerals 40 (1) to 40 (6) indicate modules, numerals 42 (1) and 42 (2) indicate data collection devices, and numeral 43 indicates a data collection control device, respectively.

Further, symbol (a) indicates a shared bus, symbol Tol indicates a data collection signal line, symbol (C1) indicates a data collection timing signal line, and symbol (d+ indicates a control signal).

Note that the data collection signal line (bl is connected to each module 40 (
1) to 40 (6) through the shared bus (a) to data collection devices 42 (1), 42
(2), and the data collection timing signal line (C) uses the signal of the shared bus fa).

Further, the control signal (d) starts/stops data collection, and also controls the plurality of data collection devices 42(1), 42(2).
) shows a data collection control signal for providing a reference time to data between ) and a data bus signal for extracting data.

In this example, data collection devices 42 (1), 42 (2
) is installed outside the modules 40(1) to 40(6), but the processing idea is the same even when installed inside.

In addition, in this example, the data collection devices 42(1) and 42(2) are
two modules 40(1), 40(2),
40 (4) and 40 (5), and two modules 40 (3) and 40 (6), respectively.

When performing data tracing of the modules 40(1) to 40(6) that are handling each task in the above-described manner,
The data collection devices 42 (1) and 42 (2) corresponding to the modules 40 (1) to 40 (6) are controlled by the control signal (d) from the data collection control device 43 that has confirmed the data collection timing signal line (C). , starts data tracing and collects all trace data of each operation process until a stop instruction is given.

The data collection control device 43 extracts trace data of a predetermined task from all the collected trace data,
The extracted trace data of the predetermined task will be analyzed.

[Problem that the invention seeks to solve]

In the data collection method described above, it is not possible to collect trace data only for a specific task, and it is not possible to collect trace data only for a specific task.
~40 Regarding (6), trace data must also be collected, and necessary task data must be extracted and analyzed from it.

For this reason, data collection devices 42 (1), 42 (
2) is required, and therefore, it is necessary to adopt a method of adding it as an external independent functional module due to the configuration.

In addition, modules 40(1) to 40(6) that share tasks
), data collection devices 42(1), 42(2)
) must also be plural, and therefore a data collection control device 43 is also required to synchronously control them.

Furthermore, such conventional methods require a function (internally built into the data collection control device 43) to extract the task data necessary for analysis from a large amount of collected trace data, resulting in cost and operational problems. There are various problems.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG.
n) and a common bus (a) that connects each other.

In addition, one module 1(n) among modules 1(0) to 1(n) functions as a shared memory, and task control for each unit work (task) of data processing is performed on this shared memory module 1(n). The task control block 14 (
0) to 14(m) are created and held.

Further, the task control blocks 14(0) to 14(m) are
The trace control information area 17 includes a trace object display flag bit 17a, and a race control word.

[Effect]

Each module 1 (other than shared memory module 1 (n)
0) to Hn-I) are task control blocks 14(0) on shared memory module 1(n) to perform task processing.
) to 14(m).

Task-compatible task control blocks 14 (0) to 14 (
When the trace target display flag bit 17a in the control information area 17 constituting part m) is set to 11'',
The task is traced according to the contents indicated by the trace control word.

On the other hand, if the trace target display flag and the foot 17a are "0", tracing is not performed as the task is not to be traced, so that tracing only a specific task can be done efficiently with a simple configuration. It becomes possible to do so.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

In this embodiment, the module 1(i) other than the shared memory module 1(n) is a microprocessor (MPU).
31, a control memory (CS) 32, a trace data memory area 33, and a bus control circuit 34.

The shared memory module 1(n) also has a bus control circuit 52.
and a shared memory 52, the shared memory 52 consisting of a task control block area 52a and a data area 52b.

In this embodiment, an example is taken in which there are three task control blocks 14(0) to 14(2) corresponding to tasks.

Module 1(i) is a microprocessor (MPtl
) 31 and the bus control circuit 34, the data in the data area 52b on the shared memory 52 is read out, and the data is stored as control data in the task control block area 52a (task control blocks 14(0) to 14(2)). data in the internal control information area 17).

At this time, if the trace target display flag bit 17a on the control data in the task control block area 52a is set to "1", the data address, processing content, etc. indicated by the trace control word in the control information area 17, etc. The trace information of control memory (CS) in module 1(i) 3
The data is recorded in a trace data memory area 33 provided in a part of 2.

Note that the above-mentioned tracing is not performed for the module whose trace target display flag 17a is set to "0". Furthermore, as a condition for tracing, it is assumed that tracing is mainly performed for the module in which an error has occurred.

The trace data collected in this way is transmitted to modules 1(0) to 1(n-1)(
(shown in FIG. 1).

In the above method of the present invention, a plurality of modules 1(0) to
Even when 1(n) processes multiple tasks simultaneously in a time-sharing manner, it is possible to efficiently (collect) trace data limited to a specific process.

Furthermore, since the memory for collection can be minimized to the necessary minimum, it becomes easy to incorporate the data collection function into the device, thereby making it possible to improve maintainability.

〔Effect of the invention〕

According to the present invention as described above, tracing of only a specific task can be efficiently performed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1(0) to 1(n-1), 40(1) to 40(6) are modules, 1(n) is a shared memory module, 14(0) to 14(m) are task control blocks, 17 is a trace control information area, 17a is a trace target display flag bit, 31 is a microprocessor (MPU), 32 is a control memory (CS), 33 is a trace data area, 34.51 is a bus control wholesale circuit, 42 (1 ), 42 (2) is a data collection device, 4
3 is a data collection control device, 52 is a shared memory, 52a is a task control block area, and 52b is a data area. Kizenguchika's 4 + Satsuki Sun Moon Pro...Thorn Flash 1 Diagram

Claims (1)

[Claims] A plurality of functional modules (1(0) to 1(n)) are interconnected via a common bus ((a)), and the plurality of functional modules (1(0) to 1(n)) are connected to each other via a common bus ((a)). In a data processing device in which one of 1(n)) functions as a shared memory, task control blocks (14(0) to 14(m)) that perform task control for each unit work (task) of data processing are The functional module (1(n)) that functions as a shared memory
a trace control information area (17) is provided in the task control block (14(0) to 14(m)), and the multiple function module (1(0)) having different functions is
~1(n)) is the task control block (14(0)~
14(m)), the trace target display flag bit (17a) is set in the trace control information area (17) to analyze the operation of the data processing devices that share processing. A task tracing method characterized in that the functional module (1(i)) determines this trace target display flag bit (17a) and performs data tracing when it is valid.