JPS63173375A - Schottky junction type field-effect transistor - Google Patents

Schottky junction type field-effect transistor

Info

Publication number
JPS63173375A
JPS63173375A JP667187A JP667187A JPS63173375A JP S63173375 A JPS63173375 A JP S63173375A JP 667187 A JP667187 A JP 667187A JP 667187 A JP667187 A JP 667187A JP S63173375 A JPS63173375 A JP S63173375A
Authority
JP
Japan
Prior art keywords
drain
layer
active layer
ohmic electrode
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP667187A
Other languages
Japanese (ja)
Inventor
Hideki Kitahata
北畑 秀樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP667187A priority Critical patent/JPS63173375A/en
Publication of JPS63173375A publication Critical patent/JPS63173375A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve a breakdown strength of gate.drain, by providing, on the N-type operating layer on the drain side, a drain Schottky metal layer wherein a part of the surface at least is covered by an ohmic electrode and which is electrically connected to an N<+> type active layer. CONSTITUTION:On a semi-insulative gallium arsenide substrate 1, an N<+> active layer 3 is formed in an N-type operating layer 2 and a source.drain region by an ion implantation method. After a tungsten silicide layer is formed on the whole surface, a gate electrode 4 composed of tungsten silicide is formed on the N-type operative layer 2 by a dry etching method, and at the same time, a drain Schottky metal layer 5 is formed in the vicinity of a boundary between the N-type operating layer 2 of the drain side and the N<+> type active layer 3. After a passivation film 7 covering the gate electrode 4 is formed, an ohmic electrode 6 composed of AuGe.Ni is formed in the source.drain region and alloyed. At this time, the ohmic electrode 6 on the drain side is formed so as to lap on the upper part of the drain Schottky metal layer 5 formely formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はショットキー接合型電界効果トランジスタに関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Schottky junction field effect transistor.

〔従来の技術〕[Conventional technology]

ソース・ドレイン領域にn+化活性層に有するショット
キー接合型電界効果トランジスタのゲー1へ・ドレイン
間の耐圧を向上させる為に、従来は第3図に示すように
、ゲート電極4とオーミック電極6の間隔、又はゲート
電極4とn+型活性層3Aの間隔を広げてオフセット構
造をとる方法が一般に用いられていた。
In order to improve the breakdown voltage between the gate 1 and the drain of a Schottky junction field effect transistor having an n+ active layer in the source/drain region, conventionally a gate electrode 4 and an ohmic electrode 6 are used as shown in FIG. Generally, a method has been used in which an offset structure is formed by increasing the distance between the gate electrode 4 and the n+ type active layer 3A.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、オーミック電極6は通常リフトオフ法に
より形成される為、エッチ付近の加工状態は比較的荒れ
ており、この部分に電界集中点(ホットスポット)が形
成され易く、ゲート・ドレイン間の耐圧のばらつきが大
きくなる。また、ゲート電極4とオーミック電極6又は
n+型活性層3Aの間隔をあまり大きくとるとチャネル
抵抗が増大し、素子の特性が劣化するという問題点があ
る。
However, since the ohmic electrode 6 is usually formed by a lift-off method, the processing condition near the etch is relatively rough, and electric field concentration points (hot spots) are likely to be formed in this area, resulting in variations in breakdown voltage between the gate and drain. becomes larger. Furthermore, if the distance between the gate electrode 4 and the ohmic electrode 6 or the n+ type active layer 3A is too large, the channel resistance increases and the characteristics of the device deteriorate.

本発明の目的は、上記問題点を除去し、ゲート・ドレイ
ン間の耐圧の向上したショットキー接合型電界効果I・
ランジスタを提供することにある。
The object of the present invention is to eliminate the above-mentioned problems and to improve the breakdown voltage between the gate and drain.
The purpose is to provide transistors.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のショットキー接合型電界効果トランジスタは、
半絶縁性基板上に形成されたn型動作層とn+化活性層
に、このn+化活性層に接して形成されたオーミック電
極とを有するショットキー接合型電界効果トランジスタ
であって、ドレイン領域側の前記n型動作層上に形成さ
れ、前記オーミック電極に少くとも表面の一部を覆われ
、かつ前記n+化活性層に電気的に接続するドレイン・
ショットキー金属層を設けたものである。
The Schottky junction field effect transistor of the present invention includes:
A Schottky junction field effect transistor having an n-type active layer formed on a semi-insulating substrate, an n+ active layer, and an ohmic electrode formed in contact with the n+ active layer, the transistor having a drain region side. a drain formed on the n-type active layer, at least a part of the surface of which is covered by the ohmic electrode, and electrically connected to the n+ active layer;
A Schottky metal layer is provided.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.

第1図において、半絶縁性のガリウム砒素基板1上にイ
オン注入法により、n型動作層とドレイン及びソース領
域にn+化活性層に形成する。次に全面にタングステン
シリサイド層を形成した後、ドライエツチング法により
n型動作層2の上部にタングステンシリサイドよりなる
ゲー1へ電極4を形成すると同時にトレイン側のn型動
作層2とn+型活性層3の境界付近上に、ドレイン・シ
ョットキー金属層5を形成する。そして、ゲート電極4
を覆うSiO□からなるパッシベーション膜7を形成後
、リフトオフ法によりソース及びドレイン領域に、A 
u G e・Niからなるオーミック電極6を成形して
合金化を行なう。このときドレイン側のオーミック電極
6は先に形成したトレイン・ショットキー金属層5の上
部に重なるように形成する。以下、ソース電極8及びド
レイン電極8Aを形成して、ショットキー接合型電界効
果トランジスタを完成させる。
In FIG. 1, an n-type active layer and an n+ active layer are formed in the drain and source regions on a semi-insulating gallium arsenide substrate 1 by ion implantation. Next, after forming a tungsten silicide layer on the entire surface, an electrode 4 is formed on the gate 1 made of tungsten silicide on the top of the n-type active layer 2 by dry etching, and at the same time, the n-type active layer 2 and the n+ type active layer on the train side are formed. A drain Schottky metal layer 5 is formed near the boundary of 3. And gate electrode 4
After forming a passivation film 7 made of SiO□ covering the
An ohmic electrode 6 made of uGe.Ni is formed and alloyed. At this time, the ohmic electrode 6 on the drain side is formed so as to overlap the top of the previously formed Train Schottky metal layer 5. Thereafter, a source electrode 8 and a drain electrode 8A are formed to complete a Schottky junction field effect transistor.

このように構成された第1の実施例においては、ドレイ
ンの接続はゲート電極4に近い側がショッI−キー接続
となっているため、オーミック接続に比べ抵抗が高く、
またドレイン・ショットキー金属層5の加工をドライエ
ツチングにより行なっている為リフトオフ法のみでオー
ミック電極6を形成してトレイン接続を形成した場合に
比べて、ゲ−1−電極側のエツジ部分の加工荒れは少な
くなっており、電界集中点(ホットスポット)も形成さ
れにくくなっている。従ってドレインゲート間の耐圧は
向上したものとなる。
In the first embodiment configured in this way, the drain connection is a Schott I-key connection on the side closer to the gate electrode 4, so the resistance is higher than that of an ohmic connection.
Furthermore, since the drain Schottky metal layer 5 is processed by dry etching, the edge portion on the gate 1-electrode side is processed less than when the ohmic electrode 6 is formed using only the lift-off method to form a train connection. Roughness has decreased, and electric field concentration points (hot spots) are less likely to form. Therefore, the breakdown voltage between the drain and gate is improved.

第2図は本発明の第2の実施例の断面図セある。FIG. 2 is a sectional view of a second embodiment of the invention.

この第2の実施例ではガリウム砒素基板1上にイオン注
入やエピタキシャル成長等により形成したn型動作層2
上にショットキー金属を成長させ、その後ドライエツチ
ング法によりゲート電極4及びドレイン・ショッ)−キ
ー金属層5を同時に形成する。その後n”型活性層3を
エピタキシャル成長法により形成するが、このときドレ
イン側のn1型活性層3はドレイン・ショットキー金属
層5に対し自己整合的に成長させる。以後のプロセスは
第1の実施例と同様である。
In this second embodiment, an n-type active layer 2 is formed on a gallium arsenide substrate 1 by ion implantation, epitaxial growth, etc.
A Schottky metal is grown thereon, and then a gate electrode 4 and a drain Schottky metal layer 5 are simultaneously formed by dry etching. Thereafter, an n'' type active layer 3 is formed by epitaxial growth, and at this time, the n1 type active layer 3 on the drain side is grown in a self-aligned manner with respect to the drain Schottky metal layer 5.The subsequent process is performed in the first embodiment. Similar to the example.

このように構成された第2の実施例においては、n+型
活性層3かn型動作層2上に形成されてドレイン・ショ
ットキー金属層5と接続されているため、短チヤネル効
果が起きず、かつゲート・ドレイン間の耐圧が向上する
という利点がある。
In the second embodiment configured in this way, the short channel effect does not occur because it is formed on the n+ type active layer 3 or the n type operating layer 2 and is connected to the drain Schottky metal layer 5. , and has the advantage that the withstand voltage between the gate and drain is improved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ショットキー接合型電界
効果トランジスタのドレイン側のn型動作層上に、オー
ミック電極に少くとも表面の一部を覆われ、かつn+化
活性層に電気的に接続するドレイン・ショットキー金属
層を設けることにより、ゲート・ドレイン間の耐圧を向
上させることができる効果がある。
As explained above, the present invention provides a Schottky junction field effect transistor on which the n-type active layer on the drain side is covered at least a part of the surface with an ohmic electrode and is electrically connected to the n+ active layer. By providing the drain Schottky metal layer, the breakdown voltage between the gate and drain can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の第1及び第2の実施例の断
面図、第3図は従来のショットキー接合型電界効果トラ
ンジスタの一例の断面図である。 1・・・ガリウム砒素基板、2・・・n型動作層、3・
・・n+化活性層に4・・・ゲート電極、5・・・ドレ
イン・ショットキー金属層、6・・・オーミック電極、
7・・・パッシベーション膜、8・・・ドレイン電極、
8A・・・ソース電極。 箭i’Il −含恭iっ
1 and 2 are cross-sectional views of first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of an example of a conventional Schottky junction field effect transistor. DESCRIPTION OF SYMBOLS 1... Gallium arsenide substrate, 2... N-type operating layer, 3...
... n+ active layer, 4... gate electrode, 5... drain Schottky metal layer, 6... ohmic electrode,
7... Passivation film, 8... Drain electrode,
8A...source electrode.箭i'Il - 恭itsu

Claims (1)

【特許請求の範囲】[Claims] 半絶縁性基板上に形成されたn型動作層とn^+化活性
層と、該n^+化活性層に接して形成されたオーミック
電極とを有するショットキー接合型電界効果トランジス
タにおいて、ドレイン領域側の前記n型動作層上に形成
され、前記オーミック電極に少くとも表面の一部を覆わ
れ、かつ前記n^+化活性層に電気的に接続するドレイ
ン・ショットキー金属層を設けたことを特徴とするショ
ットキー接合型電界効果トランジスタ。
In a Schottky junction field effect transistor having an n-type active layer and an n^+ active layer formed on a semi-insulating substrate, and an ohmic electrode formed in contact with the n^+ active layer, the drain A drain Schottky metal layer is formed on the n-type active layer on the region side, at least a part of the surface is covered with the ohmic electrode, and is electrically connected to the n^+ active layer. A Schottky junction field effect transistor characterized by:
JP667187A 1987-01-13 1987-01-13 Schottky junction type field-effect transistor Pending JPS63173375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP667187A JPS63173375A (en) 1987-01-13 1987-01-13 Schottky junction type field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP667187A JPS63173375A (en) 1987-01-13 1987-01-13 Schottky junction type field-effect transistor

Publications (1)

Publication Number Publication Date
JPS63173375A true JPS63173375A (en) 1988-07-16

Family

ID=11644834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP667187A Pending JPS63173375A (en) 1987-01-13 1987-01-13 Schottky junction type field-effect transistor

Country Status (1)

Country Link
JP (1) JPS63173375A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273937A (en) * 1988-01-08 1993-12-28 Kabushiki Kaisha Toshiba Metal semiconductor device and method for producing the same
US5376812A (en) * 1989-04-12 1994-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2010278137A (en) * 2009-05-27 2010-12-09 Sharp Corp Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277682A (en) * 1975-12-24 1977-06-30 Fujitsu Ltd Manufacture of semiconductor device
JPS546777A (en) * 1977-06-17 1979-01-19 Nec Corp Field effect type transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277682A (en) * 1975-12-24 1977-06-30 Fujitsu Ltd Manufacture of semiconductor device
JPS546777A (en) * 1977-06-17 1979-01-19 Nec Corp Field effect type transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273937A (en) * 1988-01-08 1993-12-28 Kabushiki Kaisha Toshiba Metal semiconductor device and method for producing the same
US5376812A (en) * 1989-04-12 1994-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2010278137A (en) * 2009-05-27 2010-12-09 Sharp Corp Semiconductor device

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