JPS63173154A - System for reading out timer simultaneously in multplex processor system - Google Patents

Abstract

PURPOSE:To confirm whether or not each processor execute a processing in a correct order relation, by reading out the value of the timer of each processor simultaneously corresponding to a bit of command information outputted from a command information generating means, and storing it in a timer register. CONSTITUTION:A multiplex processor system is provided with plural processors 1, 2, and 3 having the same functions, and a controller 4 which controls each processor. The controller 4 supplies the bit of command information to the timer registers 102, 202, and 302 of the processors 1-3 appropriately via signal line 5 to confirm whether or not each processor executes respective processing in the correct order relation. As a result, the register 102, 202, and 302 can read out and stored the values of the timer 101, 201, and 301 simultaneously corresponding to the bit of a command information. Stored timer values are supplied to and compared at the controller 4, and when the difference of the timer values is less than a prescribed value, it is possible to confirm that each processor can execute the processing in the correct order relation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for simultaneously reading timer values in a multiprocessor system in which timer values of a plurality of processors constituting the multiprocessor system are simultaneously read.

(Prior Art) In a multiprocessor system, processor system, or information processing device consisting of a plurality of processors, each processor has an independent timer, and each processor executes control operations according to the value of each timer. If the difference between the values of each timer exceeds a certain value, the order of processing operations executed by each processor may be reversed.

Therefore, in order to check whether each processor can or is executing its processing operations in the correct order, it is necessary to read the timer values of each processor as appropriate and compare these values. be.

(Problem to be Solved by the Invention) Conventionally, the timer values of each processor constituting a multiprocessor system are read separately for each processor, so it is impossible to stop the operation of all timers. In order to read the values of all timers, the values of each timer must be read one by one, which causes a difference in the read time of each timer, and each processor executes its processing with the correct time relationship. In order to confirm whether or not this is possible, there is a problem in that the shift in read time must be taken into account. Another method is to stop the timers of all processors at the same time and read the values of each timer at the same time. With this method, there is no need to take into account the difference in read time, but it does have the problem of having to temporarily stop all processors. There is.

The present invention has been made in view of the above, and an object of the present invention is to provide a timer in a multiprocessor system that can simultaneously read the timer values of each processor without stopping the processors or causing time lag. The purpose of the present invention is to provide a method for reading values simultaneously.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the timer value simultaneous reading method in a multiprocessor system of the present invention reads the timer values of a plurality of processors constituting the multiprocessor system. As shown in FIG. 1, this is a simultaneous reading method for reading out timer values at the same time, and as shown in FIG. The present invention includes a command information generation means 13 for outputting command information, and a timer value storage control means 15 for controlling the timer values of each processor to be simultaneously read out and stored in the timer registers 11 in response to the command information. This is the summary.

(Operation) In the simultaneous timer value reading method in the multiprocessor system of the present invention, control is performed such that the timer values of each processor are simultaneously read out and stored in the timer register in response to command information issued from the command information generation means. are doing.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a configuration diagram of a multiprocessor system to which a timer value simultaneous reading method according to an embodiment of the present invention is applied. The multiprocessor system shown in the figure has a plurality of processors 1.2.3 having the same function and a controller 4 for controlling each of these processors.

Each processor has a timer 101, 201.30, respectively.
1 and timer registers 102, 202, and 302 that store the value of the timer, respectively. Each timer register stores the value of the corresponding timer, but this storage operation is such that when command information output from the controller 4 is supplied via the signal line 5, the value of the timer at that point in time is read out. It is stored in the timer register.

That is, the controller 4 appropriately sends command information to each processor 1.
2.3 timer registers 102.202.302. As a result, each timer register 102, 202.3
02 can read and store the corresponding timer values at the same time in response to the command information.

The timer values of each processor stored in each timer register in this way are supplied to the controller 4 and compared.
It is checked whether the difference between each timer value is less than or equal to a predetermined value. As a result, if the difference between the timer values is less than or equal to a predetermined value, it is confirmed that the processes of each processor can be executed in the correct order.

FIG. 3 shows another embodiment of the invention.

In this embodiment, each processor 1.2 performs the output operation of command information performed by the controller 4 in the embodiment shown in FIG.
．． 3 can be carried out. Specifically, the storage operation of each timer value performed by the output operation of the command information described above is performed because each instruction execution unit 103, 203, and 303 provided in each processor stores the timer values of all processors. This is done by executing the command.

That is, when an instruction for storing the timer values of all processors is executed in the instruction execution unit 103 of any one of the processors 1.2.3, for example, processor 1, the instruction execution of the processor 1 is executed. Part 10
3 supplies command information for storing the timer value to each timer register 102.202.302 of each processor 1.2.3 via the signal line 6, and each timer register 102, 202.302 stores the corresponding timer value. In response to command information, the corresponding timer value is read and stored.

Note that this operation is not limited to the processor 1, but can also be performed by an instruction executed by the instruction execution unit of any of the other processors 2 and 3, and all processors may have this function. Of course, only some processors may have it.

[Effects of the Invention] As explained above, according to the present invention, the timer values of each processor are controlled to be read out simultaneously and stored in the timer register in response to the command information output from the command information generation means. Therefore, there is no difference in the time when the timer value appears one after another, and there is no need to stop the processor.
It is possible to check whether each processor can execute processing in the correct order.

[Brief explanation of the drawing]

FIG. 1 is a diagram corresponding to claims of the present invention, FIG. 2 is a configuration diagram of a multiprocessor system to which a timer value simultaneous reading method according to an embodiment of the present invention is applied, and FIG. 3 is a diagram corresponding to another embodiment of the present invention. 1 is a configuration diagram of a multiprocessor system to which such a timer value simultaneous reading method is applied. FIG. 1-3... Processor, 4... Controller, 11... Timer register, 13... Command information output means, 15... Timer value storage control means, 101-103... Timer, 102- 302...Timer register. Agent Patent Attorney Yasuo Miyoshi Figure 1

Claims (2)

[Claims] (1) A simultaneous timer value reading method in a multiprocessor system in which timer values of multiple processors constituting the multiprocessor system are read simultaneously, the method comprising a timer register provided in each processor and used to store the timer values. , a command information generation means for outputting command information for simultaneously reading the timer values of each processor; and a timer controlling the timer values of each processor to be read simultaneously and stored in the timer registers in response to the command information. 1. A method for simultaneously reading timer values in a multi-processor system, characterized by comprising: value storage control means. (2) The command information generation means is provided in at least one of the processors, and the command information generated from the command information generation means provided in any of the processors is used to set the value of the timer of each processor to the timer register. 2. A method for simultaneously reading timer values in a multiprocessor system according to claim 1, characterized in that the timer values are controlled to be stored in each of the multiprocessor systems.