JPS6317256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic semiconductor integrated circuit and a PLL (Phase Locked Loop) type FM stereo demodulation circuit using the monolithic semiconductor integrated circuit.

The PLL type FM stereo demodulation circuit essentially solves the frequency drift and phase shift of subcarriers, and is a voltage-controlled oscillator circuit (hereinafter referred to as VCO).
) is oscillated at a frequency around 76KHz, and this output is divided twice using a 1/2 divider circuit to lower the frequency to 38KHz and 19KHz. By comparing the output and the 19KHz pilot signal included in the composite signal using a phase detection circuit to form an error signal, converting this into DC using a loop filter and controlling the above VCO via a DC amplifier circuit, The oscillation output of the VCO is precisely 76KHz, synchronized with the 19KHz pilot signal.

The oscillation frequency of the above VCO was set to 76KHz because
It is difficult to obtain the 38KHz switching signal with a duty of 50% required for stereo demodulation with the VCO output as it is, so by passing the above 76KHz through a 1/2 frequency divider circuit, the above switching signal (38KHz) can be obtained.
It forms the

The VCO is composed of a CR oscillation circuit, and in order to adjust the free run frequency to around 76 KHz, a monitor terminal is provided to output the oscillation circuit or the frequency-divided output to the outside.

The above adjustment is performed by adjusting the time constant of the CR time constant circuit that constitutes the VCO, which is configured as an external circuit of the monolithic semiconductor integrated circuit.

Also, when configuring an FM/AM radio receiver,
During AM reception, if the VCO is allowed to oscillate, its harmonic components will interfere with the AM reception operation, so a control input terminal is provided to stop the oscillation operation of the VCO.

It should be noted that during FM reception, it is desirable to stop the VCO during monaural broadcasting for the same reason as above, and therefore, the control terminal is necessary even if only the FM receiving circuit is used.

This invention focuses on the fact that in the monolithic semiconductor integrated circuit for FM stereo demodulation having the above configuration, there is no need to monitor the oscillation output of the VCO when the VCO is stopped, and by sharing the above terminals. This is an attempt to reduce the number of external terminals.

This invention provides a monitor terminal with a circuit that detects a voltage exceeding the monitor output signal level range and a control circuit that stops the VCO with this detection output, and forcibly sets the monitor terminal to the above voltage, thereby controlling the VCO. It is designed to also be used as a stop input terminal.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a PLL system configured in a monolithic semiconductor integrated circuit IC showing an embodiment of the present invention.
FIG. 3 is a block diagram of an FM stereo demodulation circuit.

1 is a preamplifier that amplifies the composite signal input from terminal P ₁ and sends it to the pilot via a stereo demodulation circuit 9 and a coupling capacitor C ₁ provided between external terminals P ₂ and P ₃ . The signal is input to the phase comparator circuit 2. This phase comparison output is input to the loop filter 3 provided at the external terminals P ₄ and P ₅ to convert it into DC, and the DC amplifier circuit 4
Amplify with.

5 is a VCO, which is provided with a time constant circuit ₆ via an external terminal P6 to form an oscillation frequency output of approximately 76 KHz.

7 is a 1/2 frequency divider circuit, which divides the above VCO output by 1/2.
The frequency is divided by two to form a switching signal for the FM stereo demodulation circuit 9.

8 is a 1/2 frequency divider circuit which forms a 19 KHz signal with a 90° phase difference from the pilot signal and inputs it to the phase comparison circuit 2.

As a result, the phase comparator circuit 2 forms a signal corresponding to the phase difference (frequency difference) between the 19KHz pilot signal in the composite signal and the approximately 19KHz signal that is the frequency-divided output of the VCO 5, and controls the VCO. This locks the VCO to an accurate 76KHz synchronized with the pilot signal.

That is, when locked, the phase difference between the pilot signal and the frequency-divided output becomes 90 degrees, the phase comparison output becomes zero, and the frequency of the VCO is maintained in this state.

10 is a frequency dividing circuit, which is used for pilot signal detection. That is, this frequency dividing circuit forms a 19KHz signal that is in phase with the pilot signal, and the phase comparison circuit 11 compares the phases of both to detect the presence or absence of the pilot signal, in other words, to detect stereo/monaural. .

The output of the phase comparator circuit 11 is connected to external terminals P ₉ ,
The signal is converted into DC by a loop-pass filter 12 provided at _P10 , and inputted to a lamp drive circuit 14 through a DC amplifier circuit 13 to form a lamp drive output for stereo/monaural display.

The output of the frequency divider circuit 8 is output from the external terminal _P12 , and the free run frequency of the VCO 5 is 76KHz.
A monitor signal for adjusting the time constant circuit 6 is obtained so that the time constant circuit 6 becomes close to the current value.

In this example, the monitor output terminal
P ₁₂ is provided with a voltage detection circuit 15 that detects a voltage level exceeding the monitor output level, and a control circuit 16 that uses this detection output to stop the oscillation operation of the VCO 5.
_P12 is also used as a VCO stop control input terminal to reduce the number of external terminals.

That is, by forcibly applying a voltage signal exceeding the monitor signal level to the monitor terminal _P12 from the outside, the oscillation of the VCO 5 is stopped. It should be noted that when the oscillation of the VCO 5 is stopped, there is no need to monitor the VCO output, so there is no problem even if the terminals are shared as described above. Since the detection level of the voltage detection circuit 15 is set to a predetermined voltage exceeding the monitor output level, the monitor output does not cause a VCO stop operation.

Figure 2 shows the VCO5, which is the main part of this invention,
2 is a circuit diagram showing a specific example of a voltage detection circuit 15 and a control circuit 16. FIG.

VCO 5 consists of differential transistors Q ₁ and Q ₂ whose common emitters are provided with a constant current circuit I ₀ , and a multi-collector transistor Q ₃ which forms a current mirror circuit provided at the collector of this transistor Q ₂ .
, a constant current sink circuit I′ ₀ provided at the output side collector of this current mirror transistor Q ₃ , and a constant current sink circuit between the output of the current mirror transistor Q ₃ and the constant current circuit.
A multi-emitter structure transistor Q ₄ which inputs the current difference from I′ ₀ , and a resistor R ₄ which feeds one output back to the base of the transistor Q ₁ .
Using the other output, a resistor _R3 is applied to the base of the transistor _Q2 to give a hysteresis characteristic to the reference voltage formed by the resistors _R1 and _R2 , and an external terminal _P6 is connected to the base of the transistor _Q1 . It consists of a time constant circuit including a capacitor C and a resistor _R7 connected through the capacitor C.

The operation of this circuit is that when transistor Q ₁ is on and transistor Q ₂ is off, transistor Q ₂
Because no collector current flows, transistors Q ₃ and Q ₄ are off, so no charging current flows to the time constant circuit via resistor R ₄ , and capacitor C ₂
discharges through resistor _R7 , so the base voltage of transistor _Q1 gradually decreases. At this time,
The base voltage of transistor Q ₂ is the voltage dividing resistor R ₁ ,
This is set to the voltage on the low level side formed by _R2 .

Due to the discharge of the above time constant circuit, transistor Q ₁
is off, when transistor Q ₂ is on, the current flows through mirror transistor Q ₃ to transistor Q ₄
Since the base current is supplied to
Since Q ₄ turns on and supplies charging current to capacitor C ₂ that constitutes the time constant circuit through resistor R ₄ and also supplies current to voltage dividing resistor R ₂ through resistor R ₃ , the reference The voltage is set to a high level voltage. When the base potential of transistor Q ₁ exceeds the high level reference voltage due to the above charging operation, transistor Q ₁ is turned on and transistor Q ₂ is turned off, stopping the charging operation and lowering the reference voltage to the low level side. The VCO 5 oscillates by setting and repeating the same operation.

By adding and inputting the current generated by the DC amplifier circuit 4 to the base of the transistor _Q1 , the charging/discharging time of the time constant circuit is controlled and the oscillation frequency is controlled.

The output of the VCO 5 is transmitted via Darlington type emitter follower output circuits Q ₅ , Q ₆ , R ₅ which constitute a buffer amplifier via frequency dividing circuits 7 and 8.
A monitor output is obtained from the monitor terminal _P12 .

A Zener diode Dz and a current limiting resistor _R6 , which constitute the voltage detection circuit 15, are provided to this output, and a transistor _Q7 , which constitutes the control circuit 16, which is provided at the base of the transistor _Q2 , which constitutes the VCO, is connected to the output. This is what you input.

The operation of this circuit is as follows:
The Zener voltage Vz of Dz is set to a voltage higher than the monitor output level, and a voltage exceeding the sum (V _Z + V _REQo ) of the Zener voltage Vz and the threshold voltage V _BEQ7 of the transistor Q ₇ is applied to the monitor terminal. When the voltage is applied, the Zener diode D _Z and the transistor Q ₇ are turned on and the transistor Q ₂ constituting the VCO is fixed in the off state, so that oscillation can be stopped.

Incidentally, if a voltage of about 6V is formed as the VCO stop control voltage, the VCO stop operation can be performed reliably.

In this case, since the monitor output is passed through the emitter follower circuit, the VCO stop control voltage does not have any adverse effect on the frequency divider circuit, phase detection circuit, etc.

This invention is not limited to the above embodiments, but for example
The transistor _Q7 that stops the VCO may also be one that forcibly turns off the transistor _Q2 . Further, the voltage detection circuit 15 may be of any type, such as one using a voltage comparison circuit whose reference voltage is the voltage of a Zener diode forming a stabilized power supply. Furthermore, if the monitor output is lowered by voltage division, etc., detection can be performed at a lower voltage. The control circuit for stopping the VCO can be modified in various ways depending on the specific circuit that constitutes the VCO.

Further, each circuit block constituting the PLL type FM stereo demodulation circuit can be modified in various ways.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a specific circuit diagram showing an embodiment of the main part of the invention. 1...Preamplifier, 2...Phase comparison circuit, 3...
...Loop filter, 4...DC amplifier circuit, 5...
VCO, 6... Time constant circuit, 7... Frequency divider circuit, 8
...Frequency divider circuit, 9...Stereo demodulation circuit, 10...
... Frequency divider circuit, 11 ... Phase comparison circuit, 12 ... Low pass filter, 13 ... DC amplifier circuit, 14 ...
... Lamp drive circuit, 15 ... Voltage detection circuit, 16
...control circuit.

Claims (1)

[Claims] 1 Constructed of monolithic semiconductor integrated circuits
In an FM stereo demodulation circuit, a voltage controlled oscillator circuit that forms a PLL loop and generates an output signal within a predetermined level range, or a frequency divider that responds to the output thereof, and an input that exceeds the level range of any of the above output signals. It includes a detection circuit for detecting a signal, and a control circuit for stopping the oscillation operation of the oscillation circuit in response to the output of the detection circuit, an output terminal for taking out the output signal as a monitor, and an input terminal for applying the input signal. An FM stereo demodulation circuit comprising a single terminal.