JPS63172436A - Electronic circuit tester - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial applications The present invention relates to testing of electronic circuits III.

BACKGROUND OF THE INVENTION One of the major problems in manufacturing and using conventional integrated circuits is quality. Integrated circuits are commonly used as the heart of very complex assemblies and must be checked in advance to ensure satisfactory operation in all configurations and all logical input/output situations. Otherwise, malfunctions may occur if special circumstances arise very late in use. Such malfunctions can cause significant damage, for example, when the integrated circuit is used in military, medical, or industrial equipment.

For this reason, test equipment called testers are used to check the operation of electronic circuits, and although integrated circuits are not used during normal operation, they are used to easily check that the circuits are working properly. It often includes a targeted structure.

In general, test equipment is used not only by manufacturers of integrated circuits or complex electronic circuits, but also by users who wish to retest integrated circuits they have acquired. This is because manufacturers only sample and check manufactured integrated circuits, and if a predetermined percentage of integrated circuits pass, the patch is often accepted.

In any case, it is desirable that the test device has the following characteristics.

- High speed and precision: on complex parts, a large number of tests need to be carried out, so it is desirable that the time required for each individual test be as short as possible; - easy and simple to use knee program; - modular design; , various integrated circuits can be tested using the same test equipment and
II can be implemented with as few changes as possible.

In this application, we only consider a test device that checks the operation of a bin in an electronic circuit as a whole, and do not consider a test device that tests a single bin or a unidirectional test device. This is because these devices offer the advantages associated with modular construction, but at a cost disadvantage. That is, these devices require multiple circuits on each path when testing multiple bins - eg, test vector processors, delay generating circuits.

This is because various analog reference circuits etc. must be duplicated and provided. Additionally, due to this duplication, the single-bin testing device also has the problem of not being able to reproduce test conditions. moreover,
These structures create the problem that the test vectors are stored bit by bit differently in memory, making them difficult to access by the operator.

Typically, an operator performs the following three control actions with the test equipment.

The first is a rough control called likeness control, which simply checks whether the various power supplies and input/output ports are shorted or open.

The second is parameter control, in which it is checked whether each input/output impedance is within an acceptable range for various signals. In these two IIJa operations analog values are measured and set time values are taken into account.

The time required for each individual test is typically a few milliseconds.

Approximately 500 tests are performed on an integrated circuit with 256 bins under parameter control.

The third is function control, which checks whether the circuit operation is appropriate. For this purpose we call the test vector the connection r
A series of signals shaped in terms of R and amplitude is applied to the circuit bin or bins, and it is determined whether the response to the applied signals in the other bins or bins corresponds to the desired function of the circuit. Will be checked. Also, the speed of the logic circuits is checked during function control operations. The 1ilI required for basic functional testing is typically about 100 nanoseconds and 2
A 4000-bit test is performed on an integrated circuit with 56 bins.

An example of a typical conventional test device is shown in FIG.

This device has a central processing unit t (CPU) 10, cp
The uio is connected on the one hand to a terminal 11, a printer 12 and a boat 13 which is used to form communication links with other devices such as, for example, a host computer. Also CP
U10 is also connected, for example, to a bus 10 for transmitting and receiving data to and from various elements of the test equipment.

The circuit to be tested is plugged into the test equipment (not shown).
and are connected via the circuit mounting board 15. These boards have input/output terminals corresponding to the bins of devices to be tested. Each of these terminals is connected to a particular circuit board called an electronic pin 16. Figure 1 shows one of them.

This circuit board actually consists of a set of circuit boards arranged in a ring shape. These circuit boards 16 contain on the one hand bidirectional links to the test vector memory 17 and links to the terminals of the circuit mounting board 15, and on the other hand a common circuit 19.19' providing reference voltages and time delays.
These common circuits are connected to bus 14. Each electronic bin 16 comprises an amplitude and time shaping circuit which adjusts the signal provided by the memory 17 to reference values provided by circuits 19 and 19'. The circuit mounting board 15 consists of a buffer impedance circuit and a switch, which switches and connects the pin to be tested to the electronic bin or to the central measuring circuit unit 18 which supplies current and measures the voltage.

The components 15.16.17.18.19.19' are each programmed for satisfactory operation and then connected to the common bus 14. Each of these elements, or a subset of these elements, has a unique address by which signals sent from the bus to these elements are identified and characteristic signals detected by CPU 10 are routed back onto the bus. Ru.

The above description of conventional test equipment is very general; it simply includes a CPU, a common bus, and circuit units connected in parallel and with different addresses that perform the basic functions of the test equipment. This is only because the main purpose of the explanation was to show the configuration of the conventional test equipment equipped with the test equipment.

Problem to be Solved by the Invention In the test device having the above configuration, the circuit unit 15.1
6.18.19.19' and the operations applied to these circuit units must necessarily be relatively slow, for example on the order of a few milliseconds to tens of milliseconds. On the other hand, the memory containing the test vectors sent to or from the circuit to be tested must be read and written at very fast speeds, typically on the order of a few tenths of a nanosecond. be.

In fact, the read/write speed of a memory must be comparable to the maximum design speed of the circuit under test if the high frequency operation of the circuit is to be checked. Therefore, C
The PU 10 connects to the test vector memory 17 via the bus 14.
must operate at very high speeds. This memory 1
7 is a large-scale memory having a capacity of several gigabytes, for example.

Therefore, conventional test equipment has used sophisticated means to maximize this operating speed. However, since bus 14 carries a large number of circuits between a plurality of circuit units, it is very busy and therefore has a priori limited transmission speed. Said measures therefore required very complex technical solutions.

The central circuit 1 also supplies time signals used as reference signals for phase locking to various circuit boards (electronic bins 16).
If 9' is used, a problem arises in that the amount of delay varies from pin to pin depending on the length of the wire used, resulting in systematic errors. This wire length problem cannot be ignored in such a MIN circuit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a test device having a configuration that makes it possible to increase the operating speed of a test vector memory.

Another object of the invention is to provide a test device which improves the link between the circuit being tested and the logic portion of the test circuit to achieve the highest t-durality.

Yet another object of the present invention is to provide a test device capable of producing highly accurate phase reference signals.

Means for Solving Problems The objects and advantages of the present invention described above are as follows: A connecting circuit board connected to each terminal of a circuit to be tested; and a signal shaping means connected to the input terminals of the connecting circuit board. n circuit boards called electronic bins; a single test vector memory unit that stores all the test vectors supplied to the circuit under test and the test vectors supplied from the circuit under test; The vector memory unit is simultaneously managed by a memory management unit connected to the CPU independently of other circuit units and an address processor that operates aperiodically with respect to the CPU. This is achieved by an electronic circuit testing device characterized by the following.

In one embodiment of the invention, the test apparatus further includes a central analog measurement circuit unit, each electronic bin on the same circuit board suitably delaying and timing the test vectors transmitted through the electronic bin. It comprises: a programmable latch circuit; a circuit for generating the delay; a niprogrammable amplitude shaping circuit; and a multiplexing circuit for connecting the circuit to be tested to said circuit or to an analog central measurement circuit unit.

By connecting the test vector memory with its own address processor and its own memory control path
It becomes possible to operate the PU independently of the common bus very quickly.

By including this time-delayed reference circuit in the electronic bin, a highly accurate reference signal is obtained for each electronic bin.

Also, by providing these elements in each electronic bin, a very high degree of modularity is obtained.

Embodiments The above and other objects, features and advantages of the present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a diagram showing a test apparatus according to the present invention in comparison with the conventional test apparatus shown in FIG. 1, and clearly shows the difference in structure.

Referring to FIG. 2, the test equipment includes a cpuio and a terminal 1.
1, a printer 12, and a communication bus 13. However, the connections between CPU 10 and the various test circuit units are different.

Although FIG. 2 clearly shows a comparison with the apparatus shown in FIG. 1, it will be understood that there are clear differences in the configurations of these apparatuses. The device of FIG. 2 further includes a test vector memory 17, an electronic bin 16 and a central measurement unit 1.
8. The common bus 20 then only performs "slow" operations, called peripheral operations, and does not directly control the test vector memory.

Therefore, the cpuio does not communicate directly with the memory 17, but rather via a link 21, such as a serial link R8232C with a specific memory management unit (MMU) 22. A special address processor 23 enables specific programmable addressing to be performed in memory. All of these circuit components can be commercially available products. For example, as MMU22, Motorola M6
809 can be used and AMC can be used as an address processor.
A processor called AM2910 commercially available from Kobore-5Jyson can be used. This AM2910 processor is capable of very high addressing speeds of over 10 MHz. This processor works with a variable frequency clock,
It is also possible to vary the test sequence speed in some cases.

Therefore, the memory surface that stores the test vectors is checked or O-
It is shared by the MMU 22, which performs memory addressing, and the processor 23, which performs memory addressing and discharges test vectors at a high speed selected according to test specifications.

In addition to such general configuration changes, the present invention further provides specific configuration assemblies formed to perform various functions on the circuit boards that make up the test equipment.

This special configuration will be explained in detail in FIG. 3, but this portion is also already shown in FIG.

In this configuration, the block 19' that provides a time delay to each bin shown in FIG. 1 is not provided. This circuit is included in electronic bin 16. In addition, the electronic bottle is a circuit mounting board 1
Personalization board 2 rather than collaborating with 5
Collaborate with 4. The personalization circuit board 24 does not include any programmable active switches, only the wiring elements that electromechanically connect the bins of the circuit under test to the electronic bins 16. The programmable active switch is in this case included in an electronic bin. As a result, the central measurement unit 18 is directly connected to the electronic bin.

FIG. 3 is a block diagram showing the configuration of the test device according to the present invention by function. cpuio is shown with the same reference numerals as in Figure 2, although the symbol is different, and bus 20
is called a configuration bus, and it can be seen that the MMU 22, address processor 23, and vector memory 17 cooperate with the link 21. Vector memory 17
are organized into channels, each of which is connected to a corresponding electronic bin 16. Each electronic bin 16 comprises, inter alia, timing and delay time setting means 30, means 31 for setting the amplitude of the test vectors to be exchanged, and a multiplexer 36. The link between the test vector memory 17 and the board 16 operates in the - direction to generate the test vector signal (TES).
T) and moves in the other direction to receive and receive the analysis test vector (ANAL). This analysis test vector (ANAL) is retrieved from the controlled circuit and transmitted to a vector memory where it is compared with the expected response and stored.

The time setting circuit 30 mainly has a pair of latches 40, 41 on a path in the TEST direction, and a pair of latches 42, 43 on a path in the A/AL direction (FIG. 4). The first latch 40, 42 provides timing for the address processor 23 with respect to the clock C1. The second latch 41, 43 is also supplied via the configuration bus 20 with the output signal of the delay circuit 19' programmed by the control line 32. Second latch 41.4
3 adds a delay to the signal output from the vector memory and the signal output from the electronic bin based on the speed clock C1 from the address processor 23.

The arrangement of providing the programmable delay circuit in each electronic bin does not make the test equipment more complex than a conventional arrangement in which the delayed reference signal is provided by a single circuit 19'. This is because these delay circuits are relatively simple - using a traditional central delay circuit would force the use of a high-speed multiplexing circuit for each electronic bin; This is because the circuit is actually more difficult to construct than the delay circuit.

The configuration of the present invention avoids parasitic delays due to transmission line lengths and intervening components (multiplexers, etc.), making programming easier.

The level setting circuit 31 is an impedance array made up of ordinary transistors, and is supplied with an output signal from the level reference circuit 19 programmed by the control signal 33 via the configuration bus 20.

This circuit 31 converts the logic signal from the test memory into a voltage pulse having a voltage level varying between a high level and a low level determined by the level reference circuit 19. This circuit 31 also converts the voltage signal from the bin being tested on the return trip into a logic signal by comparing it to a reference value programmed by circuit 19.

Multiplexer 36 switches and connects the test circuit bins to the electronic bin circuit or to the central measurement circuit 18.

When the test apparatus is in the functional control mode, each electronic bin 16 is directly connected to the burnerization board 24.

This personalization board 24 according to the invention includes wiring for connection to the circuit to be tested.

The multiplexer 36 also returns the output of the personalization board to the central measurement circuit 18 for initial Ill II, ie, likeness control and parametric control. The current and voltage measurements in this case are carried out in an analog manner, and for this purpose a digital/analog converter and an analog/digital converter are provided in the central measuring circuit 20 for communication on the bus 20.

FIG. 4 shows the main elements of the electronic bin divided into transmission directions. Of these, the period and delay time setting block 30 is as already explained. On the other hand, block 31 is TESTh
High and low signal levels VIH and VI in the opposite signal path
It has an operational amplifier 44 which determines L according to the value output from block 19. This block 19 also supplies high and low comparison levels VoH and VOL to comparators 45 and 46 for analyzing the signals returned from the circuit under test. The multiplexer 36 is represented by a two-way switch 47, which switches the personalization to other circuits of the electronic bin or to the central measurement circuit 1.
Connect to 8.

Another advantage provided by the present invention is that it allows the production of test equipment that is less expensive to use. This is particularly due to the fact that the multiplexers 36 are distributed and formed on the electronic bins.

In contrast, in conventional VtI, the multiplexer is provided on the circuit mounting board 15. Multiplexers are expensive because they include a large number of relays and require the user to use a specific circuit mounting board for each type of circuit they wish to test. With the device according to the invention, it is sufficient for the user to replace the personalization board, which has expensive components and only has a connector attached. Additionally, although the personalization board associated with the test equipment architecture of the present invention is simple and purpose-specific, it is possible to test a variety of integrated circuits if the mechanical bin arrangement is common. .

To summarize, the electronic circuit testing device according to the present invention includes a connecting circuit board (34) connected to each terminal of a circuit to be tested, and an electronic bin configured with signal shaping means and connected to the input terminals of the connecting circuit board. n circuit boards called (16)
and a single test vector memory unit (17) for storing all test vectors supplied to and from the circuit under test.
A vector memory unit is connected to the CPU (10) and a memory management unit (22) which is connected to the CPU independently of other circuit units. and an address processor (23) that operates aperiodically.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the test device according to the present invention, FIG. 2 is a diagram showing the configuration of the test device according to the present invention, FIG. 3 is a diagram showing the configuration of the test device according to the present invention from another aspect, and FIG. The figure is a block diagram of an electronic bin according to the invention having a bidirectional transmission path. 10... Central processing unit (CPU), 11... Terminal,
12...Printer, 1 boat, 14.20...
Bus, 15--Circuit mounting board, 16--Electronic bin, 17--Test vector memory, 18--Central measurement circuit, 19--Reference voltage circuit, 19'--8 extension circuit , 21... link, 22... MMU, 23...
Address processor, 24--personalization board, 30--timing and delay time tm setting means, 31--test vector amplitude setting means, 32.33
...Line, 36...Multiplexer, 40-43...
Latch, 44... operational amplifier, 45.46... comparator, 47... switch. Jyogon on page I21 (no changes in 8j) Procedure 1B original book (method) 1. Indication of the case 1988 Patent Application No. 234707 2, Name of the invention Electronic circuit testing device 3, Person making the amendment Relationship to the case Patent applicant address Saint-Egrape, France 38120
Le Fontanil Cornon Lu de Ref.
Tronschard (no street address) Name: Draxy Niss N.R. Representative: Yves DeVui, 124, Agent telephone number: 03 (263) No. 3271 (Representative) December 22, 1988 (Delivery date) 6. Drawings subject to amendment . 7. Contents of the amendment: The engraving of the drawings (no changes in content) will be supplemented as shown in the attached sheet.

Claims (1)

[Scope of Claims] (1) A connecting circuit board (34) connected to each terminal of the circuit to be tested; n pieces called electronic pins constituted by signal shaping means and connected to input terminals of the connecting circuit board a circuit board (16); a single test vector memory unit (17) for storing all test vectors supplied to and from the circuit under test; the entire apparatus and external links; A vector memory unit is connected to a memory management unit (22) that is connected to the CPU independently of other circuit units.
) and an address processor (23) that operates aperiodically with respect to a CPU (10). (2) It further has a central analog measurement circuit unit (18), each electronic pin (16) is on the same board, and adjusts the timing by suitably delaying the test vector transmitted through the electronic pin. A programmable latch (30; 41-43) and a circuit (19) that generates the delay.
'), a programmable amplitude shaping circuit (31), and a multiplexing circuit (36) for connecting the circuit to be tested to said circuit or to the analog central measuring circuit (18) unit.
A test device according to claim 1, characterized in that it has: