CN113742260A - Address scrambler generating device and method for memory test - Google Patents
Address scrambler generating device and method for memory test Download PDFInfo
- Publication number
- CN113742260A CN113742260A CN202111307391.8A CN202111307391A CN113742260A CN 113742260 A CN113742260 A CN 113742260A CN 202111307391 A CN202111307391 A CN 202111307391A CN 113742260 A CN113742260 A CN 113742260A
- Authority
- CN
- China
- Prior art keywords
- address
- scrambler
- generator
- scrambling
- algorithm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses an address scrambler generating device and method for memory test. The address scrambler generating device comprises an address generator for outputting a physical address representing a target device-under-test memory cell to the address scrambler; the address scrambler is used for screening out a logic address corresponding to a physical address representing a target device under test storage unit from address scrambling data prestored by the address scrambler and outputting the logic address to a DUT board; a scrambler algorithm generator to generate address scrambling data; the input of the scrambler algorithm generator is connected with the address scrambler and is the physical address of a plurality of arbitrary storage units; the output of the scrambler algorithm generator is all logical addresses corresponding to the physical addresses of each memory cell and is written to the address scrambler. Therefore, when the method is used for testing, the test graphic file only needs to perform automatic algorithm address generation according to the physical address, does not need to care about specific logical address mapping, and improves the readability of the test graphic file.
Description
Technical Field
The invention relates to an address scrambler generator and method for memory test, belonging to the fields of integrated circuit automatic test equipment, semiconductor manufacture, instrument and meter, digital signal and memory chip test.
Background
For design reasons, memory chips do not have a one-to-one correspondence between the physical location address of the memory cell and the logical address provided for external access by the user.
The existing test method is mainly based on two types of test equipment: the first type is a test device with an algorithmic Pattern Generator (APG for short), and the second type is a test device without an APG.
For testing a memory chip, an Algorithm Pattern Generator (APG) of a testing device performs address generation according to the physical location address of a memory cell, which may result in that the physical memory cell accessed by the address generated by the APG is not an expected physical cell, thereby resulting in that the testing purpose cannot be achieved. In addition, for a test device with APG, during testing, mapping correspondence between physical addresses and logical addresses is generally realized by connecting address test channels given by ATE to physical pins of a device under test at a DUT board according to the mapping relationship between the physical addresses and the logical addresses of the memory device. This method requires that a plurality of different versions of the test pin card design of the DUT board be generated according to various mapping situations. Management and maintenance are difficult, and the cost of testing is too high due to the high cost of the Prober Card (test pin Card) and the generation of multiple versions.
For a test device without APG, a special test pattern file is usually written, a segment of test pattern is written for each memory cell, and the physical addresses of each memory cell to be tested in the corresponding test pattern are described one by one according to the logical addresses. This method is also acceptable for small memories (EEPROMs, embedded memories, etc.) because there are few Memory cells. For large memories (Flash, DDR, etc.), too many memory cells (up to millions to billions of cells) result in too large test pattern files, which results in poor readability and maintainability, and the pattern depth of general test equipment cannot meet the requirements of such test methods.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a logical address and physical address mapping solution based on an address scrambler. By the method, address mapping between the test pattern and different DUTs can be realized without modifying the test pattern file and the DUT board connection scheme; meanwhile, a more complex memory address generation method is realized through a scrambler algorithm generator.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
an address scrambler generation device for memory testing, comprising:
an address generator for outputting a physical address representing a target device-under-test memory cell to an address scrambler;
the address scrambler is used for screening out a logic address corresponding to a physical address representing a target device under test storage unit from address scrambling data prestored by the address scrambler and outputting the logic address to a DUT board;
a scrambler algorithm generator to generate address scrambling data;
the input of the scrambler algorithm generator is connected with the address scrambler and is the physical address of a plurality of arbitrary storage units; the output of the scrambler algorithm generator is all logical addresses corresponding to the physical addresses of the storage units and is written into the address scrambler;
in the memory unit of the address scrambler, the inputs and outputs of the scrambler algorithm generator are stored in a one-to-one matching mode to form the address scrambling data.
Preferably, the input and output of the scrambler algorithm generator satisfy an address scrambling algorithm to form the address scrambling data, the address scrambling algorithm being a computational expression expressing a relationship between the input and output of the address scrambler.
Preferably, the address scrambler comprises a multiplexer and a scrambling random access memory;
the input of the scrambler algorithm generator is connected to a scrambler RAM through a multiplexer;
the output of the scrambler algorithm generator is written into a scrambled random access memory for storage;
the input of the scrambler algorithm generator and the output of the scrambler algorithm generator are stored in corresponding units of the scrambler random memory in a one-to-one correspondence manner;
the physical address which is generated by the address generator and is used for representing the storage unit of the target device under test is connected to the scrambling random access memory through the multiplexer, so that the logic address which corresponds to the physical address which is used for representing the storage unit of the target device under test is screened out from the corresponding unit of the scrambling random access memory and is output to the DUT board.
Preferably, the number of the multiplexers and the scrambling random access memory in the address scrambler is matched with the bit width of the address generator.
Another technical object of the present invention is to provide an address scrambler generating method for memory test, comprising the steps of:
step one, pre-storing address scrambling data in an address scrambler
Step 1.1, edit Address scrambling Algorithm
Editing an address scrambling algorithm in a scrambler algorithm generator;
step 1.2, output all logical addresses corresponding to scrambler algorithm generator inputs
Inputting physical addresses of a plurality of arbitrary storage units into a scrambler algorithm generator, and outputting all logical addresses corresponding to the physical addresses of the storage units through the processing of an address scrambling algorithm in the scrambler algorithm generator;
step 1.3, write the logical address into the random access memory of the scrambling of the address scrambler
Writing all the logic addresses obtained by the operation in the step 1.2 into a disturbing random access memory of an address scrambler and storing the logic addresses;
step 1.4, connect input of scrambler algorithm generator to scramble RAM
Connecting the physical addresses of all storage units participating in the operation of the scrambler algorithm generator in the step 1.2 to a scrambler random access memory through a multiplexer, matching all the logical addresses written in advance in the step 1.3, and storing the physical addresses in corresponding storage units;
in the random access memory, the input and output of each scrambler algorithm generator which are matched one by one form the address scrambling data;
step two, testing
Step 2.1, outputting the physical address representing the target storage unit of the device under test
Starting an address generator to output physical addresses representing the storage unit of the target device under test to a multiplexer and a scrambling random access memory of an address scrambler in sequence;
step 2.2, outputting the logical address corresponding to the physical address of the target storage unit of the device under test
The method comprises the steps that a scrambling random access memory screens out a logic address matched with a physical address of a storage unit of a target device under test from prestored address scrambling data according to a received physical address of the storage unit of the target device under test, and then outputs the logic address to a DUT board;
step 2.3, outputting the corresponding logic address to ATE through the DUT board;
and 2.4, judging by the ATE according to the logic address input by the DUT board.
Based on the technical purpose, compared with the prior art, the invention has the following advantages:
the method has the advantages that: the test graphic file only needs to perform automatic algorithm address generation according to the physical address, does not need to care about specific logical address mapping, and improves the readability of the test graphic file.
The method has the advantages that: the same test pattern file can be adapted to different target devices (the same chip can be packaged into different shapes, and the sequence and the number of the provided physical address access pins can be different), so that the maintainability of the test pattern file is improved.
The method has the advantages that: a plurality of memory chips of the same die can share one test pin card, so that the test cost is reduced.
Drawings
FIG. 1 schematically illustrates an address scrambler generation device in accordance with one embodiment of the present invention;
FIG. 2 shows a flow chart illustrating the steps of a method of an embodiment of the invention;
in fig. 1: 11. an X address generator; 12. a Y address generator; 13. an address scrambler; 13-1, a multiplexer; 13-2, disturbing the random access memory; 14-a scrambler algorithm generator; 15-target device under test.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The relative arrangement of the components and steps, expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
As shown in fig. 1 and fig. 2, the present invention provides an address scrambler generating device for memory test, comprising: an address generator, an address scrambler, and a scrambler algorithm generator, wherein:
the address generator is used for outputting a physical address representing a target storage unit of the device under test to the address scrambler;
the address scrambler is used for screening out a logic address corresponding to a physical address representing a target device under test storage unit from address scrambling data prestored by the address scrambler and outputting the logic address to a DUT board;
the scrambler algorithm generator is used for generating address scrambling data;
the input of the scrambler algorithm generator is connected with the address scrambler and is the physical address of a plurality of arbitrary storage units; the output of the scrambler algorithm generator is all logical addresses corresponding to the physical addresses of the storage units and is written into the address scrambler; the input and the output of the scrambler algorithm generator meet the address scrambling algorithm:
in the memory unit of the address scrambler, the inputs and outputs of the scrambler algorithm generator are stored in a one-to-one matching mode to form the address scrambling data.
The address scrambler algorithm is a calculation expression for expressing the relationship between the input (X, Y) and the output O of the address scrambler, wherein the address scrambler comprises an X address scrambler and a Y address scrambler, X is the input X corresponding to the address scrambler, and Y is the input corresponding to the Y address scrambler. For example: for X Scable Ram (X address scrambler), assuming the DUT has X [15:0], Y [15:0] address bit widths, the following equation is set:
O[15:1] = X[15:1];
O[0] = X[0] ^ X[1];
both equations cover the correspondence between O [15:0] and X [15:0], and when each X can be enumerated by the software address obfuscator, the value of O corresponds to, for example:
X O
0x0000 0x0000
0x0001 0x0001
0x0002 0x0003
0x0003 0x0002
0x0004 0x0004
0x0005 0x0005
0x0006 0x0007
......
the value of O in the case of 65535 is required to be enumerated above. Then, each O value is written into each cell corresponding to the X Scramble Ram, namely, the address scrambling data is formed. The data generation method of the Y Scramble Ram (Y address scrambler) is the same.
Preferably, the address scrambler comprises a multiplexer and a scrambling random access memory; the input of the scrambler algorithm generator is connected to a scrambler RAM through a multiplexer; the output of the scrambler algorithm generator is written into a scrambled random access memory for storage; the input of the scrambler algorithm generator and the output of the scrambler algorithm generator are stored in corresponding units of the scrambler random memory in a one-to-one correspondence manner; the physical address which is generated by the address generator and is used for representing the storage unit of the target device under test is connected to the scrambling random access memory through the multiplexer, so that the logic address which corresponds to the physical address which is used for representing the storage unit of the target device under test is screened out from the corresponding unit of the scrambling random access memory and is output to the DUT board.
Preferably, the number of the multiplexers and the scrambling random access memory in the address scrambler is matched with the bit width of the address generator.
Based on the address scrambler generating device, the invention provides an address scrambler generating method for memory test, which comprises the following steps:
step one, pre-storing address scrambling data in an address scrambler
Step 1.1, edit Address scrambling Algorithm
Editing an address scrambling algorithm in a scrambler algorithm generator;
step 1.2, output all logical addresses corresponding to scrambler algorithm generator inputs
Inputting physical addresses of a plurality of arbitrary storage units into a scrambler algorithm generator, and outputting all logical addresses corresponding to the physical addresses of the storage units through the processing of an address scrambling algorithm in the scrambler algorithm generator;
step 1.3, write the logical address into the random access memory of the scrambling of the address scrambler
Writing all the logic addresses obtained by the operation in the step 1.2 into a disturbing random access memory of an address scrambler and storing the logic addresses;
step 1.4, connect input of scrambler algorithm generator to scramble RAM
Connecting the physical addresses of all storage units participating in the operation of the scrambler algorithm generator in the step 1.2 to a scrambler random access memory through a multiplexer, matching all the logical addresses written in advance in the step 1.3, and storing the physical addresses in corresponding storage units;
in the random access memory, the input and output of each scrambler algorithm generator which are matched one by one form the address scrambling data;
step two, testing
Step 2.1, outputting the physical address representing the target storage unit of the device under test
Starting an address generator to output physical addresses representing the storage unit of the target device under test to a multiplexer and a scrambling random access memory of an address scrambler in sequence;
step 2.2, outputting the logical address corresponding to the physical address of the target storage unit of the device under test
The method comprises the steps that a scrambling random access memory screens out a logic address matched with a physical address of a storage unit of a target device under test from prestored address scrambling data according to a received physical address of the storage unit of the target device under test, and then outputs the logic address to a DUT board;
step 2.3, outputting the corresponding logic address to ATE through the DUT board;
and 2.4, judging by the ATE according to the logic address input by the DUT board.
Example 1
Fig. 1 discloses in detail an embodiment of the invention, which is exemplified by a 16-bit X, Y address generator. Wherein:
both the X address generator 11 and the Y address generator 12 are 16 bits. Each address generator (X address generator 11 or Y address generator 12) is mainly composed of a 16-bit Arithmetic Logic Unit (ALU) and a number of 16-bit counters (Counter). An ALU and Counter may be used to implement a 16-bit address generation according to an algorithm that characterizes the physical address of the target device-under-test memory location.
The address scramblers 13 include an X address scrambler and a Y address scrambler. Each address scrambler (X address scrambler or Y address scrambler) is composed of a multiplexer 13-1, and a 64KX16 Scramble Random Access Memory (SRAM) 13-2. The output of the SRAM, which is the output of the address scrambler, is connected to the DUT.
The scrambler algorithm generator 14 is a software algorithm generator, and a user can input an address scrambling algorithm, namely a relational formula between an X address, a Y address and an output O, on software:
the software algorithm generator automatically exhausts the corresponding logic address (output O) under each X or Y address input condition according to the address scrambling algorithm, and writes the logic address into a scrambling random access memory (Scramble Ram). Simultaneously, the X address and the Y address which need to participate in the operation are connected to the Scramble Ram through a multiplexer according to an address scrambling algorithm, so that each X address, each Y address and corresponding logic address are stored in the scrambling random access memory in a one-to-one matching mode
Therefore, different X addresses and Y addresses select corresponding units of the Scramble Ram and output stored logic addresses, and automatic conversion from X or Y physical addresses generated by the ALU to output logic addresses is realized.
A Device Under Test (DUT) 15, i.e., a memory Under Test.
The above scheme is an automatic solution for how to convert physical addresses to logical addresses, and is not limited to a specific bit width of the address generator, or the number of address generators, for example: the method is also applicable to the condition of an X, Y and Z address generator with 24bit width, and only the multiplexer and the SRAM in the scrambler are expanded according to the 24bit width.
Example 2
FIG. 1 is a flow chart of a method of an embodiment of the invention, which is based on an address scrambler generating device for memory test of the embodiment. Including the following modifications:
step one, pre-storing address scrambling data in an address scrambler
Step 1.1, a user edits an address scrambling algorithm formula in an address scrambler to form a scrambling algorithm generator;
step 1.2, inputting a physical address X, Y of a 16-bit arbitrary storage unit into an address scrambling algorithm generator, wherein the scrambling algorithm generator exhaustively exhausts corresponding logical addresses under all input conditions according to an address scrambling algorithm formula;
step 1.3, downloading all logic addresses into the Scramble Ram by software;
step 1.4, software sets each multiplexer, and connects all physical addresses X, Y participating in operation to the Scramble Ram;
step two,
Step 2.1, starting a test, generating a physical address required by the test through an X, Y address generator, and inputting the physical address into an address scrambler;
step 2.2, the Scramble Ram of the address scrambler outputs the stored corresponding logic address to the DUT according to the physical address generated in step 2.1;
2.3, the DUT outputs data of the corresponding logic address to the ATE;
and 2.4, judging whether the test passes or not by the ATE according to the output data of the DUT, and informing a Handler (processor) or a Prober (test pin) to carry out Pass/Fail sorting.
Claims (6)
1. An address scrambler generation device for memory testing, comprising:
an address generator for outputting a physical address representing a target device-under-test memory cell to an address scrambler;
the address scrambler is used for screening out a logic address corresponding to a physical address representing a target device under test storage unit from address scrambling data prestored by the address scrambler and outputting the logic address to a DUT board;
a scrambler algorithm generator to generate address scrambling data;
the input of the scrambler algorithm generator is connected with the address scrambler and is the physical address of a plurality of arbitrary storage units; the output of the scrambler algorithm generator is all logical addresses corresponding to the physical addresses of the storage units and is written into the address scrambler;
in the memory unit of the address scrambler, the inputs and outputs of the scrambler algorithm generator are stored in a one-to-one matching mode to form the address scrambling data.
2. The address scrambler generating device of claim 1, wherein the inputs and outputs of said scrambler algorithm generator satisfy an address scrambling algorithm to form said address scrambling data.
3. The address scrambler generating device for memory testing of claim 2, wherein the address scrambling algorithm is a computational expression expressing the relationship between the input and output of an address scrambler.
4. The address scrambler generating device of claim 3, wherein said address scrambler comprises a multiplexer and a scrambling random access memory;
the input of the scrambler algorithm generator is connected to a scrambler RAM through a multiplexer;
the output of the scrambler algorithm generator is written into a scrambled random access memory for storage;
the input of the scrambler algorithm generator and the output of the scrambler algorithm generator are stored in corresponding units of the scrambler random memory in a one-to-one correspondence manner;
the physical address which is generated by the address generator and is used for representing the storage unit of the target device under test is connected to the scrambling random access memory through the multiplexer, so that the logic address which corresponds to the physical address which is used for representing the storage unit of the target device under test is screened out from the corresponding unit of the scrambling random access memory and is output to the DUT board.
5. The address scrambler generating device for memory test of claim 4, wherein the number of multiplexers and scramblers in said address scrambler matches the bit width of the address generator.
6. An address scrambler generation method for memory testing, comprising the steps of:
step one, pre-storing address scrambling data in an address scrambler
Step 1.1, edit Address scrambling Algorithm
Editing an address scrambling algorithm in a scrambler algorithm generator;
step 1.2, output all logical addresses corresponding to scrambler algorithm generator inputs
Inputting physical addresses of a plurality of arbitrary storage units into a scrambler algorithm generator, and outputting all logical addresses corresponding to the physical addresses of the storage units through the processing of an address scrambling algorithm in the scrambler algorithm generator;
step 1.3, write the logical address into the random access memory of the scrambling of the address scrambler
Writing all the logic addresses obtained by the operation in the step 1.2 into a disturbing random access memory of an address scrambler and storing the logic addresses;
step 1.4, connect input of scrambler algorithm generator to scramble RAM
Connecting the physical addresses of all storage units participating in the operation of the scrambler algorithm generator in the step 1.2 to a scrambler random access memory through a multiplexer, matching all the logical addresses written in advance in the step 1.3, and storing the physical addresses in corresponding storage units;
in the random access memory, the input and output of each scrambler algorithm generator which are matched one by one form the address scrambling data;
step two, testing
Step 2.1, outputting the physical address representing the target storage unit of the device under test
Starting an address generator to output physical addresses representing the storage unit of the target device under test to a multiplexer and a scrambling random access memory of an address scrambler in sequence;
step 2.2, outputting the logical address corresponding to the physical address of the target storage unit of the device under test
The method comprises the steps that a scrambling random access memory screens out a logic address matched with a physical address of a storage unit of a target device under test from prestored address scrambling data according to a received physical address of the storage unit of the target device under test, and then outputs the logic address to a DUT board;
step 2.3, outputting the corresponding logic address to ATE through the DUT board;
and 2.4, judging by the ATE according to the logic address input by the DUT board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111307391.8A CN113742260A (en) | 2021-11-05 | 2021-11-05 | Address scrambler generating device and method for memory test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111307391.8A CN113742260A (en) | 2021-11-05 | 2021-11-05 | Address scrambler generating device and method for memory test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113742260A true CN113742260A (en) | 2021-12-03 |
Family
ID=78727495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111307391.8A Pending CN113742260A (en) | 2021-11-05 | 2021-11-05 | Address scrambler generating device and method for memory test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113742260A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023221620A1 (en) * | 2022-05-18 | 2023-11-23 | 南京宏泰半导体科技股份有限公司 | Templated memory test pattern generator and method |
| CN117612592A (en) * | 2024-01-23 | 2024-02-27 | 悦芯科技股份有限公司 | Burst code winding system for vector generator of memory chip tester |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5428767A (en) * | 1992-07-30 | 1995-06-27 | Rohm Co., Ltd. | Data retention circuit |
| CN101021783A (en) * | 2007-03-19 | 2007-08-22 | 中国人民解放军国防科学技术大学 | Stream data-oriented resequencing access storage buffering method and device |
| CN102682853A (en) * | 2011-03-16 | 2012-09-19 | 南亚科技股份有限公司 | Test system and test method for memory |
| CN103793333A (en) * | 2012-10-30 | 2014-05-14 | 北京兆易创新科技股份有限公司 | Nonvolatile memory encrypting method and device and nonvolatile memory |
| CN111462807A (en) * | 2019-01-18 | 2020-07-28 | 华邦电子股份有限公司 | Error correction code memory device and code word access method |
-
2021
- 2021-11-05 CN CN202111307391.8A patent/CN113742260A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5428767A (en) * | 1992-07-30 | 1995-06-27 | Rohm Co., Ltd. | Data retention circuit |
| CN101021783A (en) * | 2007-03-19 | 2007-08-22 | 中国人民解放军国防科学技术大学 | Stream data-oriented resequencing access storage buffering method and device |
| CN102682853A (en) * | 2011-03-16 | 2012-09-19 | 南亚科技股份有限公司 | Test system and test method for memory |
| CN103793333A (en) * | 2012-10-30 | 2014-05-14 | 北京兆易创新科技股份有限公司 | Nonvolatile memory encrypting method and device and nonvolatile memory |
| CN111462807A (en) * | 2019-01-18 | 2020-07-28 | 华邦电子股份有限公司 | Error correction code memory device and code word access method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023221620A1 (en) * | 2022-05-18 | 2023-11-23 | 南京宏泰半导体科技股份有限公司 | Templated memory test pattern generator and method |
| CN117612592A (en) * | 2024-01-23 | 2024-02-27 | 悦芯科技股份有限公司 | Burst code winding system for vector generator of memory chip tester |
| CN117612592B (en) * | 2024-01-23 | 2024-04-26 | 悦芯科技股份有限公司 | Burst scrambling system for vector generator of memory chip tester |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6668347B1 (en) | Built-in self-testing for embedded memory | |
| US5138619A (en) | Built-in self test for integrated circuit memory | |
| US5475694A (en) | Fuzzy multiple signature compaction scheme for built-in self-testing of large scale digital integrated circuits | |
| CN109524055B (en) | Method for positioning failure bit of memory based on SOC ATE and test system | |
| CN113742260A (en) | Address scrambler generating device and method for memory test | |
| US6618826B1 (en) | Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs | |
| JPS62266638A (en) | Testing of functioning performance separately at a pluralityof memory sites for memorizing digital data | |
| CN105911462A (en) | Automatic test apparatus for functional digital testing of multiple semiconductor integrated circuit devices | |
| KR20000013809A (en) | Built in self test device using linear feedback shift register | |
| EP1763677B1 (en) | Circuit arrangement and method of testing an application circuit provided in said circuit arrangement | |
| JP2002203399A (en) | Advance memory tester having post decoding function | |
| CN101165502B (en) | Tester simultaneous test method | |
| US6438048B1 (en) | Nonvolatile memory and high speed memory test method | |
| US6675336B1 (en) | Distributed test architecture for multiport RAMs or other circuitry | |
| US5566186A (en) | Test control device | |
| US6675337B1 (en) | Built-in self verification circuit for system chip design | |
| JP4863547B2 (en) | Semiconductor integrated circuit device with built-in BIST circuit | |
| CN117031256B (en) | Chip testing system and method | |
| KR100319711B1 (en) | Built in self test circuit with debugging function | |
| JP4183854B2 (en) | Memory test equipment | |
| JPH06102327A (en) | Memory built-in type semiconductor integrated circuit and logical design method therefor | |
| JP2943521B2 (en) | Test vector generation method and test vector generation device | |
| US6421810B1 (en) | Scalable parallel test bus and testing method | |
| KR20010004112A (en) | Apparatus for testing internal rom in chip | |
| Su et al. | Comprehensive interconnect BIST methodology for virtual socket interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211203 |
|
| RJ01 | Rejection of invention patent application after publication |