CN117612592B - Burst scrambling system for vector generator of memory chip tester - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a burst scrambling system for a vector generator of a memory chip tester, which belongs to the technical field of chip testing and specifically comprises the following steps: establishing a coordinate system on a storage chip, generating a logic address (X, Y), converting the logic address into a physical address (u, v) by using an address matching algorithm, storing the physical addresses corresponding to all X/Y address bits in advance, and storing an index relation; marking initial X and Y address bits as burst addresses, setting burst length N according to the initial physical address, performing burst operation on the Y address bits, keeping the physical address of the X address bits unchanged, and automatically adding 1 to the physical address of the Y address bits until N times are reached, and stopping; then, the physical address of the next X address bit and the physical address of the first Y address bit are obtained and used as the initial burst address of the next round, and the burst operation is repeated; the invention realizes accurate and rapid scrambling of the logic address of the memory chip.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a burst scrambling system for a vector generator of a memory chip tester.
Background
Critical to the development of the integrated circuit industry is testing, which extends throughout the process of integrated circuit design, chip fabrication, packaging, and integrated circuit application. The main purpose of the test is to ensure that the device can completely realize the functions and performance indexes specified by the design specification under severe environmental conditions. The test contents can be categorized into two main categories: parameter testing and functional testing. The parameter test is mainly direct current parameter test, wherein voltage or current is applied to a DUT pin to measure a specific parameter value; the function test is a logic test, and a test for realizing the expected logic function is realized by applying predetermined stimulus according to a vector truth table.
The types of the test chips can be classified into SOC testers, analog testers, memory testers, and the like. The storage tester is different from the common SOC tester in that the test vector is large and the information to be stored is more. In the memory chip test equipment, the generation of test vectors is different from that of the common SOC test equipment, because a large number of test vectors are needed for the memory chip test, the types and the depths of the test vectors are different, but a certain rule is followed. We use ALPG (Algorithmic Pattern Generator) to generate address and data. The address generated by APLG is a logical address and the physical address of the actual chip is not in one-to-one correspondence, the scrambling function is needed, the traditional scrambling is single data scrambling, the converted address is required to be set each time, and the scrambling module can be reached through a layer-by-layer path from the upper computer, so that the speed is low.
Disclosure of Invention
The invention aims to provide a burst scrambling system for a vector generator of a memory chip tester, which solves the following technical problems:
The address generated by APLG is a logical address and the physical address of the actual chip is not in one-to-one correspondence, the scrambling function is needed, the traditional scrambling is single data scrambling, the converted address is required to be set each time, and the scrambling module can be reached through a layer-by-layer path from the upper computer, so that the speed is low.
The aim of the invention can be achieved by the following technical scheme:
a burst scrambling system for a memory chip tester vector generator, comprising:
The address acquisition module is used for establishing a forward rectangular coordinate system by taking one end of the memory chip as an origin, generating a plurality of logic addresses (X, Y) in the memory chip, wherein the logic addresses comprise X address bits and Y address bits, the initial bits of the logic addresses are (0, 0), and acquiring an address matching algorithm of the memory chip, and the address matching algorithm is used for converting the logic addresses (X, Y) into actual physical addresses (u, v) of the memory chip;
the X address scrambling RAM is used for storing physical addresses corresponding to all X address bit logical addresses in advance, storing the index relation between any X address bit logical address and the corresponding physical address, and sequencing the logical addresses of the X address bits according to the sequence to obtain X 1,x2,...xn, wherein n is a positive integer;
The Y address scrambling RAM is used for storing physical addresses corresponding to all Y address bit logical addresses in advance, storing the index relation between any Y address bit logical address and the corresponding physical address, and sequencing the Y address bit logical addresses according to the sequence to obtain Y 1,y2,...ym, wherein m is a positive integer;
The Y address burst module is used for marking the first X address bit and the Y address bit as initial burst addresses, setting burst lengths N, N is less than or equal to m according to the physical addresses (u 1,v1) of the initial burst addresses in the scrambling RAM, performing burst on the Y address bits, keeping the physical addresses u 1 of the X address bits unchanged each time, automatically adding 1 to the physical addresses of the Y address bits, acquiring corresponding physical addresses v i in the Y address scrambling RAM, sequentially generating new physical addresses (u 1,vi), i epsilon 2, N, and stopping the burst of the round until i=N; and (3) acquiring the physical address of the next X address bit and the physical address of the first Y address bit from the X address scrambling RAM according to the sequence, generating (u j,v1) the physical address as the initial burst address of the next round, continuing the burst of the next round, wherein j represents the burst round number, j is 2, and n, until j=n, and ending all bursts of the memory chip.
As a further scheme of the invention: in the Y address burst module, if N is smaller than M, the physical address u 1 of the X address bits is kept unchanged in the next round of burst, the physical address of the Y address bits is still added with 1 automatically, the corresponding physical address v i is output in the Y address scrambling RAM, new physical addresses (u 1,vi) are generated in sequence until i=n+m, the burst ends in the present round, M is less than or equal to M, and M is the number of times of the burst in the present round.
As a further scheme of the invention: and the address acquisition module generates a logic address of the memory chip by an ALPG method.
As a further scheme of the invention: the address matching algorithm provided by the memory chip manufacturer is prestored in the X/Y address scrambling RAM.
As a further scheme of the invention: the X/Y address scrambling RAM comprises the following steps:
Physical address scrambling code data corresponding to all logical addresses are calculated in advance according to an address matching algorithm, physical address scrambling code data corresponding to X address bits are stored in an X scrambling code RAM, physical address scrambling code data corresponding to Y address bits are stored in a Y scrambling code RAM, any index relation between a logical address and the corresponding physical address is stored in the X scrambling code RAM or the Y scrambling code RAM, the logical address of the X address bits or the logical address of the Y address bits is used as an index, and the corresponding logical address is found according to the index relation and output.
As a further scheme of the invention: the X address bit and the Y address bit only represent coordinate positions, and the numerical values of physical addresses corresponding to the logic addresses of different memory chips are different.
The invention has the beneficial effects that:
(1) Under the condition that the row X address bit is determined, burst read-write can be carried out on the row Y address as a scrambling code, a burst module firstly sets burst length, then a low-order address of Y is automatically added with 1 to carry out scrambling code, after the burst is finished, if Y does not reach the maximum address, the burst is continued, after the maximum address is reached, Y becomes an initial value, then X+1, and Y burst is continued, so that a series of external operations are saved, meanwhile, only the value of the row Y is changed every time of burst, time is saved, efficiency is improved, and meanwhile, the flexibility and reliability of a system are further improved by pre-calculating the physical address and storing the physical address in a scrambling code RAM.
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The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic flow chart of the present invention;
FIG. 2 is a schematic diagram of the memory chip coordinates of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-2, the present invention is a burst scrambling system for a vector generator of a memory chip tester, comprising:
The address acquisition module is used for establishing a forward rectangular coordinate system by taking one end of the memory chip as an origin, generating a plurality of logic addresses (X, Y) in the memory chip, wherein the logic addresses comprise X address bits and Y address bits, the initial bits of the logic addresses are (0, 0), and acquiring an address matching algorithm of the memory chip, and the address matching algorithm is used for converting the logic addresses (X, Y) into actual physical addresses (u, v) of the memory chip;
the X address scrambling RAM is used for storing physical addresses corresponding to all X address bit logical addresses in advance, storing the index relation between any X address bit logical address and the corresponding physical address, and sequencing the logical addresses of the X address bits according to the sequence to obtain X 1,x2,...xn, wherein n is a positive integer;
The Y address scrambling RAM is used for storing physical addresses corresponding to all Y address bit logical addresses in advance, storing the index relation between any Y address bit logical address and the corresponding physical address, and sequencing the Y address bit logical addresses according to the sequence to obtain Y 1,y2,...ym, wherein m is a positive integer;
The Y address burst module is used for marking the first X address bit and the Y address bit as initial burst addresses, setting burst lengths N, N is less than or equal to m according to the physical addresses (u 1,v1) of the initial burst addresses in the scrambling RAM, performing burst on the Y address bits, keeping the physical addresses u 1 of the X address bits unchanged each time, automatically adding 1 to the physical addresses of the Y address bits, acquiring corresponding physical addresses v i in the Y address scrambling RAM, sequentially generating new physical addresses (u 1,vi), i epsilon 2, N, and stopping the burst of the round until i=N; and (3) acquiring the physical address of the next X address bit and the physical address of the first Y address bit from the X address scrambling RAM according to the sequence, generating (u j,v1) the physical address as the initial burst address of the next round, continuing the burst of the next round, wherein j represents the burst round number, j is 2, and n, until j=n, and ending all bursts of the memory chip.
The logical and physical addresses of a memory chip are two different address representations that play different roles in memory access.
The logical address is an address generated by the CPU for internal and programming use, and is not unique. For example, in performing C language pointer programming, the value of the pointer variable itself (& operation) is read, which is actually a logical address, which is an address (offset address) relative to the current process data segment, and does not directly correspond to an absolute physical address.
The physical address is the address loaded into the memory address register and is the real address of the memory cell. The physical address refers to the actual physical location in memory, which is directly managed by the computer hardware, and is used to mark the location of the storage unit in memory. The operating system can directly access the data in the memory through the physical address.
The function of the address scrambler is to convert a logical address into an actual physical address. In a computer, a logical address refers to an address used by a programmer, and a physical address refers to an actual address used by a CPU. Due to the manufacturing process of the manufacturer, the wafer shape, technology implementation, and other factors. In a system, logical addresses and physical addresses do not necessarily have to be in one-to-one correspondence, which requires a mechanism to translate logical addresses into physical addresses, which is called address mapping or address translation.
The logical addresses and the physical addresses are in one-to-one correspondence, and the starting points x and y of the logical addresses are 0 and 0, the corresponding physical addresses are 2 and 5, the x and y of the logical addresses are 1 and 1, the corresponding physical addresses are 3 and 6, the x and y of the logical addresses are m and n, and the corresponding physical addresses are m+2 and n+5, and the logical addresses are in one-to-one correspondence according to the rule. It should be noted that such a correspondence is only an example, and the manufacturer has various correspondences according to actual products;
We choose a simpler scrambling rule [ m+2, n+5], just by way of example, the actual scrambling rule is much more complex, m=100, n=300, assuming that the logical address x takes 0, y starts the burst from 0, the burst length is 100, then the physical address of this conversion is automatically [2,5], [2,6] … [2,104], the burst ends, the burst length and address are reset next time. If there is no burst, the converted address is set every time, the scrambling module can be reached from the upper computer through a layer-by-layer path, and if the burst length is 100, the data is required to be sent from the upper computer 100 times, so that the efficiency is greatly improved.
FIG. 1 is a flow chart of burst, setting the starting address and burst length of Y burst, then automatically adding 1 to the address, adding 1 to the burst frequency, entering a mixed large address, finding out the corresponding physical address, then outputting, judging whether the burst frequency and the burst length are equal, if not, continuing adding 1 to the address, adding 1 to the burst frequency, re-scrambling the code until the frequency is equal, and ending the burst. From the above, the time of adding 1 to the Y address is far less than the time of each fetch from the upper computer;
In another preferred embodiment of the present invention, in the Y address burst module, if N is smaller than M, the physical address u1 of the X address bit is kept unchanged in the next round of burst, the physical address of the Y address bit is still added with 1 automatically, the corresponding physical address vi is output in the Y address scrambling RAM, and new physical addresses (u 1, vi) are sequentially generated until i=n+m, and then the present round of burst ends, M is less than or equal to M, and M is the number of times of the present round of burst.
In another preferred embodiment of the present invention, the address acquisition module generates the logical address of the memory chip by an ALPG method.
ALPG (Algorithmic Pattern Generator) is an algorithm for generating test patterns. It is used to design and generate test sequences to verify the function and performance of the chip. ALPG plays an important role in chip testing and can help engineers evaluate the reliability, stability and correctness of chips.
The ALPG generates test sequences in a certain rule and order by using a specific algorithm and pattern generator. These sequences can simulate different operations and signal inputs to test the response of the chip under various conditions. ALPG can generate complex input sequences that cover various functional units and interfaces of the chip to ensure that the chip operates properly under all conditions.
The application of ALPG in chip testing can greatly improve the test efficiency and the test coverage rate. By automatically generating test sequences, ALPG may reduce the workload of manually designing test cases, and may more fully test the functionality of the chip. In addition, the ALPG can also detect potential faults and abnormal conditions by generating a random pattern, so that the reliability of chip testing is improved.
ALPG (Algorithmic Pattern Generator) when generating the logical address of the chip, it is usually generated according to the design specification, functional requirements and test strategy of the chip. It may generate the logical address of the chip by:
according to the design specification: the ALPG will first refer to the design specification of the chip, including information on internal logic structure, register allocation, memory mapping, etc. These design specifications describe the logical address ranges and access modes of the functional units inside the chip, and provide important basis for ALPG to generate logical addresses.
Consider the functional requirement: the ALPG generates corresponding test patterns according to the logic address range of the functional unit or interface to be tested, taking the functional requirements of the chip into consideration. These test patterns can cover various operations and signal inputs to verify the correctness and stability of the chip at different logical addresses.
Following a test strategy: the ALPG will follow a specific test strategy, generating the appropriate sequence of logical addresses according to the test requirements. The test policy may include sequential access, random access, special pattern coverage, etc. to ensure that the logical address space of the chip is adequately covered and tested.
Consider a specific application scenario: depending on the specific application scenario and intended use of the chip, the ALPG may generate a sequence of logical addresses that are tailored to these scenarios to simulate operation and data access in a practical application environment.
In another preferred embodiment of the present invention, the address matching algorithm provided by the memory chip manufacturer is pre-stored in the X/Y address scrambling RAM.
The matching algorithm between the Logical Address (Logical Address) and the physical Address (PHYSICAL ADDRESS) of the chip is typically implemented by a vendor-supplied Memory Management Unit (MMU).
The MMU is responsible for translating the logical addresses used by the application into physical addresses and sending these addresses to the memory controller for retrieval of the data. MMUs typically use a data structure called a "page table" to map between logical and physical addresses.
MMUs use page tables to find mappings between logical and physical addresses, translating logical addresses to physical addresses. This process involves calculation of the page table index and the intra-page offset, ultimately generating the physical address.
In another preferred embodiment of the present invention, the X/Y address scrambling RAM:
Physical address scrambling code data corresponding to all logical addresses are calculated in advance according to an address matching algorithm, physical address scrambling code data corresponding to X address bits are stored in an X scrambling code RAM, physical address scrambling code data corresponding to Y address bits are stored in a Y scrambling code RAM, any index relation between a logical address and the corresponding physical address is stored in the X scrambling code RAM or the Y scrambling code RAM, the logical address of the X address bits or the logical address of the Y address bits is used as an index, and the corresponding logical address is found according to the index relation and output.
The actual address correspondence is specified by the manufacturer, and two scrambling code RAMs are needed to be prepared, and are divided into scrambling codes X RAMs and Y RAMs as shown in FIG. 2; the actual address data is stored in the memory, and the algorithm of the actual address data is generally calculated by an internal algorithm of a manufacturer and then stored into a scrambling RAM designed by the manufacturer. The storage order is the order of logical addresses, ranging from small to large. For example, the 0 address of the X RAM stores the data Xp0, that is, the physical address corresponding to the logical address x=0 is Xp0, the 1 address stores the data Xp1, that is, the physical address corresponding to the logical address x=1 is Xp1, until the maximum address n address stores the data Xpn, that is, the physical address corresponding to the logical address x=n is Xpn.
Similarly, the data stored at the 0 address of the scrambling code Y RAM is Xp0, that is, the physical address corresponding to the logical address y=0 is Yp0, the data stored at the 1 address is Yp1, that is, the physical address corresponding to the logical address y=1 is Yp1, until the data stored at the maximum address m is Ypm, that is, the physical address corresponding to the logical address y=m is Ypm.
In another preferred embodiment of the present invention, the X address bits and Y address bits represent only coordinate positions, and the values of physical addresses corresponding to the logical addresses of different memory chips are different.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (6)
1. A burst scrambling system for a memory chip tester vector generator, comprising:
The address acquisition module is used for establishing a forward rectangular coordinate system by taking one end of the memory chip as an origin, generating a plurality of logic addresses (X, Y) in the memory chip, wherein the logic addresses comprise X address bits and Y address bits, the initial bits of the logic addresses are (0, 0), and acquiring an address matching algorithm of the memory chip, and the address matching algorithm is used for converting the logic addresses (X, Y) into actual physical addresses (u, v) of the memory chip;
the X address scrambling RAM is used for storing physical addresses corresponding to all X address bit logical addresses in advance, storing the index relation between any X address bit logical address and the corresponding physical address, and sequencing the logical addresses of the X address bits according to the sequence to obtain X 1,x2,...xn, wherein n is a positive integer;
The Y address scrambling RAM is used for storing physical addresses corresponding to all Y address bit logical addresses in advance, storing the index relation between any Y address bit logical address and the corresponding physical address, and sequencing the Y address bit logical addresses according to the sequence to obtain Y 1,y2,...ym, wherein m is a positive integer;
The Y address burst module is used for marking the first X address bit and the Y address bit as initial burst addresses, setting burst lengths N, N is less than or equal to m according to the physical addresses (u 1,v1) of the initial burst addresses in the scrambling RAM, performing burst on the Y address bits, keeping the physical addresses u 1 of the X address bits unchanged each time, automatically adding 1 to the physical addresses of the Y address bits, acquiring corresponding physical addresses v i in the Y address scrambling RAM, sequentially generating new physical addresses (u 1,vi), i epsilon 2, N, and stopping the burst of the round until i=N; and (3) acquiring the physical address of the next X address bit and the physical address of the first Y address bit from the X address scrambling RAM according to the sequence, generating (u j,v1) the physical address as the initial burst address of the next round, continuing the burst of the next round, wherein j represents the burst round number, j is 2, and n, until j=n, and ending all bursts of the memory chip.
2. The burst scrambling system for a vector generator of a memory chip tester according to claim 1, wherein in the Y address burst module, if N is smaller than M, the physical address u 1 of the X address bits is kept unchanged for the next round of burst, the physical address of the Y address bits is still automatically added with 1, the corresponding physical address v i is output in the Y address scrambling RAM, and new physical addresses (u 1,vi) are sequentially generated until i=n+m, then the burst of the present round ends, M is less than or equal to M, and M is the number of times of the burst of the present round.
3. The burst scrambling system for memory chip tester vector generator of claim 1 wherein the address acquisition module generates the logical address of the memory chip by an ALPG method.
4. The burst scrambling system for a memory chip tester vector generator of claim 1 wherein the X address scrambling RAM and the Y address scrambling RAM are pre-stored with an address matching algorithm provided by a memory chip manufacturer.
5. The burst scrambling system for use with a memory chip tester vector generator of claim 1 wherein, in the X address scrambling RAM and the Y address scrambling RAM:
According to an address matching algorithm, physical address scrambling code data corresponding to all logical addresses are calculated in advance, physical address scrambling code data corresponding to X address bits are stored in an X address scrambling code RAM, physical address scrambling code data corresponding to Y address bits are stored in a Y address scrambling code RAM, index relations between any one logical address and the corresponding physical address are stored in the X address scrambling code RAM or the Y address scrambling code RAM, and the logical address of the X address bits or the Y address bits is used as an index and is output according to the index relations.
6. The burst scrambling system for memory chip tester vector generator of claim 1 wherein the X address bits and the Y address bits represent only coordinate locations and the physical addresses corresponding to different memory chip logical addresses differ in value.
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