JPS63171034U - - Google Patents

Description

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the concept of parity generation, FIG. 2 is a diagram for explaining the parity generation method, and FIG. 3 is a diagram showing the configuration of the parity generation circuit. Block diagram, Figure 4 is the 3rd
FIG. 5 is a block diagram showing details of the P parity generation section in FIG. 3, FIG. 5 is a diagram showing details of the Q parity generation section in FIG. 3, and FIG. 6 is a timing chart for explaining the operation. 11... P parity generation unit, 12... First data selector, 13... Second data selector, 14
...Timing generation unit, 15...Q parity generation unit, 16...RAM, 17...Address counter, 21, 31...EX OR circuit (exclusive OR circuit), 22...Latch circuit, 23, 32
...Latch circuit with reset.

Claims (1)

[Scope of claims for utility model registration] One block is for multiple words, and one block is for one block.
A first error correction code is generated for each block of the original data that is transmitted as a frame and one word per block, and a second error correction code is generated for the word at the same position in each block. In the error correction code generation device that generates the error correction code, a predetermined operation is performed on the previous one-word operation result stored in the first storage circuit and the one-word original data transmitted this time. Then, the current calculation result is stored in the first storage circuit, and when the transfer of one block of original data is completed, the storage result stored in the first storage circuit is stored as the first error for one block. The first value to be retained as a correction code
selects the calculation result at the word position corresponding to the original data transmitted this time from among the calculation results for one previous block stored in the second storage circuit;
A predetermined operation is performed on the selected operation result and the original data transmitted this time, and the operation results are sequentially stored in the second storage circuit.
A second error correction code operation that holds the operation result stored in the second storage circuit as a second error correction code for the word at the same position in each block at the time when the transfer of the original data for a frame is completed. means for selecting and outputting the first error correction code stored in the first storage circuit after one block of original data has been transmitted; An error correction code generation device comprising: control means for selecting and outputting a second error correction code stored in a storage circuit;