JPS63171026U - - Google Patents
Info
- Publication number
- JPS63171026U JPS63171026U JP6195087U JP6195087U JPS63171026U JP S63171026 U JPS63171026 U JP S63171026U JP 6195087 U JP6195087 U JP 6195087U JP 6195087 U JP6195087 U JP 6195087U JP S63171026 U JPS63171026 U JP S63171026U
- Authority
- JP
- Japan
- Prior art keywords
- lines
- signal
- controller
- row
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は本考案の一実施例を示す要部回路図、
第２図は一般的なシンセサイザー受信機を示すブ
ロツク図である。
１７……信号検出回路、１８……コントローラ
、２１……入力回路、２２……スイツチングトラ
ンジスタ。
FIG. 1 is a main circuit diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a general synthesizer receiver. 17...Signal detection circuit, 18...Controller, 21...Input circuit, 22...Switching transistor.
Claims (1)
動作を行うシンセサイザー受信機であつて、すく
なくとも前記分周器の分周比を制御するためのコ
ントローラと、このコントローラからの複数の出
力線を列線とすると共に一端が前記コントローラ
の入力端子に接続された複数の信号線を行線とし
、且つ前記列線と行線との交点にスイツチが配置
された入力回路と、所定レベル以上の受信信号が
検出された際、検出信号を出力する信号検出回路
と、この信号検出回路からの検出信号及び前記コ
ントローラからのミユーテイング信号に基づき前
記入力回路の所定列線と行線間の接続状態を制御
する回路とを具備したことを特徴とするシンセサ
イザー受信機。 (2) 入力回路の所定列線と行線間の接続により
、コントローラが掃引停止モードに設定されるこ
とを特徴とする実用新案登録請求の範囲第１項記
載のシンセサイザー受信機。[Claims for Utility Model Registration] (1) A synthesizer receiver that performs channel selection by varying the frequency division ratio of a frequency divider, comprising at least a controller for controlling the frequency division ratio of the frequency divider. A plurality of output lines from the controller are used as column lines, a plurality of signal lines each having one end connected to an input terminal of the controller are used as row lines, and a switch is arranged at the intersection of the column line and the row line. a signal detection circuit that outputs a detection signal when a received signal of a predetermined level or higher is detected; and a signal detection circuit that outputs a detection signal when a received signal of a predetermined level or higher is detected; A synthesizer receiver comprising a circuit for controlling the connection state between column lines and row lines. (2) The synthesizer receiver according to claim 1, wherein the controller is set to a sweep stop mode by a connection between a predetermined column line and a row line of the input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6195087U JPS63171026U (en) | 1987-04-23 | 1987-04-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6195087U JPS63171026U (en) | 1987-04-23 | 1987-04-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171026U true JPS63171026U (en) | 1988-11-08 |
Family
ID=30895758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6195087U Pending JPS63171026U (en) | 1987-04-23 | 1987-04-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171026U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020638B2 (en) * | 1977-08-24 | 1985-05-23 | 株式会社石井鉄工所 | Assembly method of membrane inner tank in membrane type cryogenic tank |
-
1987
- 1987-04-23 JP JP6195087U patent/JPS63171026U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020638B2 (en) * | 1977-08-24 | 1985-05-23 | 株式会社石井鉄工所 | Assembly method of membrane inner tank in membrane type cryogenic tank |
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