JPS63171023A - Majority logic circuit - Google Patents

Abstract

PURPOSE:To quickly decide a majority logic by turning-on/off a constant current source corresponding to each input with a binary logic level to obtain the total sum of current outputs of constant current sources in a majority logic circuit of plural binary logic inputs. CONSTITUTION:In an example of a majority logic circuit for three-bit binary logical inputs, constant current sources 1 and 21-23 consist of bipolar transistors TRs and emitter resistances and current switches 31-33 consist of emitter-coupled logics ECLs. Current switches 31-33 are turned on or off according as input level of input terminals 61-63 are '1' or '0', and consequently, currents of current sources 21-23 are also turned on or off similarly. The current I1 of the constant current source 1 and the current I2 of each of current sources 21-23 are set to satisfy relations I1=3/2I2. At this time, the voltage of a resistance R, namely, the output of a comparator 5 having zero voltage as the reference is negative or positive according as two or more input levels out of three input levels are '0' or '1', and the input level is judged to be '0' or '1'.

Description

[Detailed Description of the Invention] 1. The present invention relates to majority logic circuits, particularly in the fields of digital communication, digital computers, and data transmission, which can be used to prevent disturbances such as code errors in digital data on the receiving side. This invention relates to a majority logic circuit for determining majority logic at high speed.

Prior art In such a majority logic circuit, an input data code string is divided into blocks of a certain length, and each block length is used as a unit to select data codes of the same logic level (binary logic level). A majority decision is made based on whether the number of items that take the level ``1'' and ``0'' exceeds a certain value.

For example, majority logic is 2/3.315.4/7゜5/9
．． Generally expressed as j/n,
For the block length n of the code string on the data receiving side, the number i of data that has the same logic level among the data contained therein
If i≧j, all received data is determined to have that value. In the data communication of Brigadier General 2, for example, the logic "
If the number i of "1" is a predetermined number j, if i≧j, all data is determined to be logical "1", and conversely, if i<j, all data is determined to be logical "0". It is generally used to assume certain events for j>i and j<i.

An example of such a conventional majority logic circuit is shown in FIG. 4, and this example shows a case of 2/3 majority logic. Out of the three logic inputs 41 to 43, two inputs are
It consists of AND gates 44 to 46 which are manually operated, and an OR gate 47 whose outputs from these three AND gates 44 to 46 are operated by three people, and a majority decision output is obtained from the output 4B of the OR gate 47.

FIG. 5 is a diagram showing a truth table of the circuit of FIG. 4, and as shown in the figure, the output logic is determined by the one with more input logic. Not only the 2/3 majority logic, but also the j/n majority logic in general can be realized with a similar circuit configuration.

However, in 2/3 majority logic, 2 of the gate circuits
The stage configuration is fine, but 315.4/7.5/9...
・When the block length of the input code becomes large, the combinational logic circuit becomes complicated, the number of circuit stages becomes multi-stage, and a hierarchical repeating structure is formed, resulting in a large number of logic circuit configurations, so the delay time increases. This has the disadvantage that it is impractical for ultra-high speed use.

OBJECTS OF THE INVENTION An object of the present invention is to provide a majority logic circuit capable of extremely high speed operation.

According to the present invention, there is provided a majority logic circuit for determining the logic level of a plurality of input signals each having a binary logic level, the majority logic circuit having a plurality of logic levels provided corresponding to each of the input signals. comprising a constant current source, and a plurality of switching means provided corresponding to each of the input signals and controlling on/off the current of the corresponding constant current source according to the binary logic level of the corresponding input signal, A majority logic circuit is obtained, characterized in that the majority decision of the logic level of the input signal is determined by the sum of the output current values of the constant current sources controlled by each of the switching means.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

The constant current source 1 has a constant current value 1, and its output current is led to the node A. A resistor 4 having a resistance value R is provided between the node A and the ground, and the voltage eA across the resistor 4 serves as the voltage of the level comparator 5.

On the other hand, the constant current sources 21 to 2n provided corresponding to the n binary input signals 61 to 6n, respectively, have a constant current value I2. Further, the current switches 31 to 3n provided corresponding to the n input signals 61 to 6n are on/off controlled by the corresponding input signals, and the current output node A of the corresponding constant current source is controlled according to the on/off state. The supply to is controlled on and off. The voltage e8 of this node A is compared to zero level by the level comparator 5, and the comparison amount cuff is derived as a majority logic output signal.

In such a configuration, the following relationship is set: I, -(1/2)n 12 ·"" (1). Here, the voltage eA at node A is expressed by the following equation.

eA = R(11-7:/(12,) ” )−・−(
2) In formula (2), (1,)'' takes either O or I2.

The n input signals 61 to 6n respectively turn on and off the corresponding n current switches 31 to 3n.
For example, it is assumed that when a logic "1" is applied as an input signal, the current switch switches to the ground side, and when a logic rOJ is applied, the current switch switches so as to lead the constant current I2 to the node A. Therefore, each current switch 31-3n is switched and controlled according to the logical value of the corresponding input signal 61-6n. For this purpose, current 1 from constant current source 1 flows into node A through resistor R to the ground side, and on the other hand, current from current sources 21 to 2n flows through resistor R to correspond to the number of logical "0"s in the input signal. A current equal to the number of currents will be drawn. Therefore, eA shown in equation (2) appears at node A. When formula (2) is rewritten using formula (1), it becomes (3), and majority logic can be determined based on the sign or minus of this eA. Therefore, in the level comparator 5, (3)
This is determined by comparing the sign of eA in the equation with the zero level.

To give a concrete example, in the case of 2/3 majority vote, n=3. j=
2, I2-1mA, Ω in R-1, I1= (1
/2)n12 = (1/2)X3X1=1.5mA
Then, the potential eA of the node A and the logic cuff (Y) for the 3-bit input signals Bl, B2, and B3 become as shown in the truth table of FIG.

FIG. 3 is a specific circuit diagram when implementing 2/3 majority logic in the embodiment of FIG. 1. In this example,
The constant current sources 1 and 21 to 23 are all constructed from bipolar transistors and their emitter resistors, and each current switch 31 to 33 is configured as an emitter-coupled transistor current switch.

In this way, the emitter-coupled so-called ECL current switch with high-speed switching characteristics controls each constant current source on and off according to the input logic level, and determines the majority vote of the input logic level according to the sum of the current values at that time. Therefore, regardless of the number of input signals, there is always only a delay time of one stage of circuit (ECL circuit), and this delay time can also be increased in speed by the ECL circuit, which is advantageous.

It should be noted that the circuit example shown in FIG. 3 is merely an example, and it is possible to construct the circuit using elements such as field effect transistors in addition to bipolar transistors, and various modifications are possible. It's obvious.

1. As described above, according to the present invention, the majority logic of the input logic level is determined in the current mode using a current switching circuit that can operate at high speed. This has the effect of allowing high-speed majority logic decisions to be made regardless of any relationship. Therefore, it is extremely suitable even when the number of inputs is large, particularly in the communication field and data processing field, which require ultra-high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a truth table for explaining the operation of the blocks in FIG. 1,
Figure 3 is a circuit diagram of a specific example of the block in Figure 1, Figure 4 is a diagram showing an example of a conventional majority logic circuit, and Figure 5 is a truth table for explaining the operation of the circuit in Figure 4. FIG. Explanation of symbols of main parts 1... Constant current source 4... Resistor

Claims (1)

[Claims] A majority logic circuit that determines the logic level of a plurality of input signals, each having a binary logic level, comprising a plurality of constant current sources provided corresponding to each of the input signals, and a plurality of constant current sources provided corresponding to each of the input signals; a plurality of switching means provided corresponding to each one and controlling on/off the current of the corresponding constant current source according to the binary logic level of the corresponding input signal, and controlled by each of the switching means. A majority logic circuit, characterized in that the majority decision of the logic level of the input signal is determined based on the sum of output current values of the constant current sources.