JPS63169827A - Binary counter - Google Patents

Abstract

PURPOSE:To select and set the number of times of counting freely by connecting optional number of counter blocks for 1-bit count having 2-stage of latch circuits in cascade and adding a circuit to set initial counter information to each counter block. CONSTITUTION:Counter blocks 1-3 connected in cascade have 2-stage of latch circuits of the same constitution, respectively. A 1st latch circuit consists of a 1st inverter 4, 1st, 2nd clocked inverters 5, 7 and 1st, 2nd transfer gates 6, 8 and the 2nd latch circuit is connected in series. A 3rd inverter 14 outputs a count signal O1 and feeds it back to the 1st latch circuit. The transfer gates 15, 16 connect an input line of the least significant bit signal I1 in the initial counter information and an input section of 1st, 2nd inverters 4, 9. 5th, 6th transfer gates 15, 16 are controlled by an initial counter information setting signal LD and 1st, 3rd inverters 5, 10 and 2nd, 4th transfer gates 8, 13 are controlled by the inverse of the signal LD. Since the data circulated by one period of the clock signal C1 is inverted by an odd number of inverters and clocked inverters, optional initial counter information is counted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter having a two-stage latch circuit.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional example of this type of counter, and FIG. 4 is a timing diagram of its operating signals.

In this conventional example, an arbitrary number of counter blocks 31, 32 .
33, etc. are connected in cascade to form a counter with a corresponding number of digits.

The counter block 31 is connected to the clocked inverter 21.
23 and an inverter 22, and a clocked inverter 24, 26 and an inverter 2.
5 and the final stage inverter 27 are connected in series, and the output of the inverter 27 is output as a count signal 011 and is also fed back to the input side of the clocked inverter 21 of the first latch circuit. Ru. The clock signal C11 is input to the clocked inverters 21.26, and the inverted signal of the clock signal Cn is input to the clocked inverters 23.24 via the inverter 28, thereby turning on the first and second latch circuits. / Turn off.

All other counter blocks 32, 33, etc. have the same configuration, and the count signal 011.012.0 of the previous stage is
13, etc. are the next stage counter blocks 32 and 33, respectively.
etc. is input as a clock signal.

Next, the operation of this conventional example will be explained first with respect to the counter block 31 with reference to FIG.

At time to, the count signal 011 is at the "HI" level, the clock signal C11 is also at the "L" level, the clocked inverter 21 is off, and the clocked inverter 2 is turned off.
4 is turned on, and the clocked inverter 21
．． It is assumed that all of the outputs of 24 are at the "L" level.

When the clock signal C11 rises at time t1, the clocked inverter 21 is turned on and its output becomes “H”.
``Although the level is inverted, the clocked inverter 24 is turned off, so its output does not change.When the clock Cn falls at time t2, the clocked inverter 21 is turned off and its output does not change, and the clocked inverter 24 is turned off. 24 is turned on and inverts its output to "H" level.

At this time, the clocked inverter 26 is off, and the count signal 011 changes to the "H" level for the first time through the clocked inverter 24 and the inverter 25.degree. 27, and is fed back to the input side of the clocked inverter 21.

Thereafter, by the same operation, the output of the clocked inverter 21 changes to the "L" level at time t3, and at time t4, the output of the clocked inverter 24 changes to the 'L' level with the falling of the clock signal C11, thus counting The signal 011 is also inverted to “L” level at time t.
Return to the initial state of o. Thereafter, by repeating the same cycle operation, a count signal On obtained by dividing the clock signal by two is obtained.

Since the count signal On mentioned above is input as a clock signal to the counter block 32 at the next stage, the count signal 012 of the counter block 32 is changed to the count signal 011.
The frequency is divided by 2, and in the same manner, the count signal Q On of the number of counter blocks is 012.013
A binary counter output consisting of , . . . is obtained.

[Problem that the invention seeks to solve]

The conventional counter described above does not have a means for setting initial counter information, so it has the disadvantage that it cannot start counting from an arbitrary count number.

(Means for Solving the Problems) In the binary counter of the present invention, each counter block includes a first inverter and a first inverter connected in series to the input side of the first inverter.
a clocked inverter and a first transfer gate, and a second clocked inverter and a second transfer gate inserted in series in a circuit that feeds back the output of the first inverter to its input terminal. a latch circuit, a corresponding second inverter similar to the first latch circuit, a third clocked inverter and a third transfer gate, a fourth clocked inverter and a fourth transfer gate; a second latch circuit configured to input the output of the first latch circuit; and a second latch circuit connected to the output side of the second latch circuit to output the count signal and input the cough signal to the first latch circuit. a third inverter that feeds back to the side; and fifth and sixth transfer gates that input the corresponding 1-bit signal in the input initial counter information to the input terminals of the first and second inverters, respectively; the fifth and sixth transfer gates are turned on by an initial counter information setting signal, and the first and third clocked inverters and the second and fourth transfer gates are turned on by an initial counter information setting signal; The transfer gate is turned on by an inverted signal of the setting signal, and when one of the first and second latch circuits performs a latching operation by a clock signal and its inverted signal, the other circuit releases the latch. The clock signal for the first stage counter block is input from the outside, and the clock signal for the second stage counter block is input from the outside.
As the clock signal for the counter blocks in the subsequent stages, the count signal output from the counter block in the previous stage is used.

(Function) With the above configuration, the binary counter of the present invention sets the initial counter information to the inverter input terminals of the first and second latch circuits of each counter block via the transfer gate before starting counting, and then outputs the clock signal. Alternatively, count signals can be used to turn on/off the transfer gates and clocked inverters of each latch circuit, and the output count signals can be fed back to the input side of the first latch circuit to start counting from arbitrary initial counter information. be able to.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a binary counter of the present invention, and FIG. 2 is an operation timing chart of this embodiment.

In this embodiment, as in the conventional example described above, an arbitrary number of counter blocks 1, 2, 3, etc. are connected via IA to form a binary counter with a corresponding number of digits.

The first latch circuit of the first stage counter block 1 is
an inverter 4, a first clocked inverter 5 and a first transfer gate 6 connected in series to the input side thereof, and a second clocked inverter 5 inserted in a circuit that feeds back the output of the first inverter 4 to its input end. , a clocked inverter 7 and a second transfer gate 8. The second latch circuit has exactly the same configuration as the first latch circuit, and has a corresponding second inverter 9.
, a third clocked inverter 10 , a third transfer gate 11 , and a fourth clocked inverter 1
2 and a fourth transfer gate 13, and are connected in series to the output side of the first latch circuit. The third inverter 14 is connected to the output side of the second latch circuit, outputs the count signal 01, and feeds back the signal 01 to the input side of the first latch circuit. The fifth and sixth transfer gates 15.16 connect the input line for receiving the least significant bit signal 11 in the initial counter information and the input portions of the first and second inverters 4.9, respectively. The fourth inverter 17 receives the input clock signal C.
Invert 1.

Note that the first transformer 77 gate 6 and the fourth clocked inverter 12 are controlled by the clock signal C1, and the second clocked inverter 7 and the third transfer gate 11 are controlled by the inverted signal of the clock signal C1, respectively. The fifth and sixth transfer gates 15.16 are connected to the initial counter information setting signal LD, and the first and third clocked inverters 5.10 and the second and fourth transfer gates 8.13 are connected to the inverter 18. Each is controlled by an inverted signal of the setting signal LD.

The counter blocks 2, 3, etc. in the second and subsequent stages all have the same configuration as the above-mentioned first stage counter block 1,
1-bit signal 1 in the corresponding initial counter information
2.13, etc., and the respective preceding stage count signals o1.02.03 etc. are branched and input as clock signals.

Next, the operation of this embodiment will be explained using FIG. 2.

In this case, regardless of the initial levels of the counter outputs o1, o2.03, etc. of each counter block 1.2.3, etc., the levels of the initial counter information 11, ■2, ■3 to be set are set to "H". , "L", and L', and the other bits are omitted.

At time to, the initial counter information setting signal LD is set to “H”.
”, in the counter block 1, the fifth and sixth transfer gates 15.16 are turned on, and the first and third clocked inverters 5.10 and the second and fourth transfer gates 8.13 are turned off. Therefore, the initial counter information 11 is placed on the input side of the first and second inverters 4.9.
is set. Therefore, the first and second inverters 4
．． The outputs of the third inverter 14 all become "L", and the output of the third inverter 14, that is, the count signal @ot becomes "H". In the counter block 2.3, a similar operation is performed so that the count signal 02.03 is the input initial counter information I2.
．． 13 are respectively output and become "L", and the counter becomes capable of counting from the set initial counter information.

At time t1, the initial counter information setting signal LD becomes “L”.
”, the fifth and sixth transfer gates 15.16
is turned off, and the first and third clocked inverters 5.
10 and second and fourth transformer 77 gates 8.13
turns on. The initial counter information setting signal LD is synchronized with the fall of the clock signal C1, and since the clock signal C1 is "L" at this time, the third transfer gate 11 is in the on state, and the first inverter 4 output (“L” level) is the third clocked inverter 1
0 and the "H" level output is input to the second inverter 9 via the third transfer gate 11, but since it is the same as the initial counter information 11 that has been set, there is no change.

When the clock signal C1 is inverted to "H" at time t2, the third transformer 77 gate 11 is turned off, the first transfer gate 6 is turned on, and the output ("H") of the third inverter 14 is turned on to the first transfer gate 11. The output of the first inverter 4 is inverted (“H′) through the gate 6, and the output of the third inverter 4 is inverted (“H′”).
The output of the clocked inverter 10 is inverted and becomes "yes".

When the clock signal C1 becomes "L" at time t3, the first transfer gate 6 is turned off and the third transfer gate 11 is turned on, so that the output ("L") of the third clocked inverter 10 becomes "L". The count signal 01 of the third inverter 14 is set to “L” through the inverter 9 of
”.

At the same time, the counter output 01 is input to the counter block 2 as a clock signal of the next stage, and its output 02 is changed to "H" by a similar operation. That is, count signal 0
3.02, Ot changes from the initial value "001" to "010".

Hereinafter, in exactly the same way as described for the conventional example, an odd number of inverters and a clocked inverter 4.5.9.
10.14, the data circulating in one cycle of the clock signal C1 is inverted, so it is possible to easily count from any initial counter information and obtain a binary counter output.

In the above explanation, an example of 3 digits was described, but by cascading any number of similar counter blocks,
Any number of digits can be counted.

〔Effect of the invention〕

As explained above, the present invention provides an arbitrary number of 1-bit counting counter blocks that are connected in cascade, each having two stages of latch circuits formed by feeding back an inverter output to an inverter input terminal through a clocked inverter and a transfer gate. By adding a circuit for setting initial counter information to each counter block, it is possible to freely select and set the count number.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the binary counter of the present invention, Fig. 2 is an operation timing diagram of the same embodiment, Fig. 3 is a circuit diagram of a conventional binary counter, and Fig. 4 is the conventional example. FIG. 2 is an operation timing diagram. 1.2.3... Counter block, 4... First inverter, 5... First clocked inverter, 6... First transfer gate, 7... Second clocked inverter. Inverter, 8... Second transfer gate, 9... Second inverter, 10... Third clocked inverter, 11... Third transfer gate, 12... Fourth clock inverter, 13... fourth transfer gate, 1
4...Third inverter, 15...Fifth transfer gate, 16...Sixth
transformer 77 gate, 17... fourth inverter, 18... inverter, It, 12, I3... initial counter information, C1...
Clock signal, LD...Initial counter information setting signal, 01, C2, 0
3...Count signal.

Claims (1)

[Claims] An n-bit binary counter in which initial counter information can be set and counter blocks that count one bit are connected in cascade, each counter block comprising a first inverter and a second inverter. The first connected in series on the input side
a clocked inverter and a first transfer gate, and a second clocked inverter and a second transfer gate inserted in series in a circuit that feeds back the output of the first inverter to its input terminal. a latch circuit, a corresponding second inverter similar to the first latch circuit, a third clocked inverter and a third transfer gate, a fourth clocked inverter and a fourth transfer gate; a second latch circuit configured to input the output of the first latch circuit; and a second latch circuit connected to the output side of the second latch circuit to output a count signal and input the signal to the first latch circuit. a third inverter that feeds back to the input side; fifth and sixth transfer gates that input the corresponding 1-bit signal in the input initial counter information to the input terminals of the first and second inverters, respectively; the fifth and sixth transfer gates are turned on by an initial counter information setting signal, and the first and third clocked inverters and the second and fourth transfer gates are turned on by an initial counter information setting signal; The transfer gate is turned on by an inverted signal of the setting signal, and when one of the first and second latch circuits performs a latching operation by a clock signal and its inverted signal, the other circuit releases the latch. This is a binary counter in which the clock signal for the first stage counter block is input from the outside, and the clock signal for the second and subsequent stage counter blocks uses the count signal output from the previous stage counter block.