JPS63169123A - Noise level measuring instrument - Google Patents
Noise level measuring instrumentInfo
- Publication number
- JPS63169123A JPS63169123A JP70587A JP70587A JPS63169123A JP S63169123 A JPS63169123 A JP S63169123A JP 70587 A JP70587 A JP 70587A JP 70587 A JP70587 A JP 70587A JP S63169123 A JPS63169123 A JP S63169123A
- Authority
- JP
- Japan
- Prior art keywords
- sine wave
- noise
- value
- period
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims abstract 2
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000008030 elimination Effects 0.000 description 4
- 238000003379 elimination reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
ディジタル正弦波を入力し、音声符号／復号化装置の雑
音量を測定する場合、符号化器の出力の、雑音を重畳し
た正弦波の値と、該出力の値を該正弦波の１／２周期遅
延させた値とを加算して、正弦波の値を打ち消して、雑
音量のみを抽出し、これの２乗平均をとることで雑音量
を測定するようにすることで、正弦波の値を取り除く回
路を、１／２周期遅延させる手段及び加算器にて構成出
来るようにし、回路規模を小さくしたものである。[Detailed Description of the Invention] [Summary] When measuring the amount of noise in a speech encoding/decoding device by inputting a digital sine wave, the value of the sine wave on which noise is superimposed at the output of the encoder and the output The value of the sine wave is added to the value delayed by 1/2 period of the sine wave, the value of the sine wave is canceled, only the amount of noise is extracted, and the amount of noise is measured by taking the root mean of this. By doing so, the circuit for removing the value of the sine wave can be configured with means for delaying 1/2 period and an adder, thereby reducing the circuit scale.
本発明は、アナログ信号とディジタル信号とのインタフ
ェースである音声符号／復号化装置（ＣＯＤ Ｅ Ｃ）
の特性を診断する雑音量測定装置の改良に関する。The present invention is an audio encoding/decoding device (CODEC) that is an interface between analog signals and digital signals.
This invention relates to an improvement of a noise amount measuring device for diagnosing the characteristics of.
音声符号化装置では、量子化雑音、電源よりの雑音等雑
音が発生するが、この雑音量を測定して音声符号／復号
化装置の特性を診断してか、この雑音量測定装置として
は回路規模が小さく出来ることが望ましい。In speech encoding devices, noise such as quantization noise and noise from the power supply is generated, but this noise amount measuring device can be used to measure the amount of noise and diagnose the characteristics of the speech encoding/decoding device. It is desirable to be able to do it on a small scale.
以下従来例を図を用いて説明する。 A conventional example will be explained below using figures.
第３図は従来例のブロック図、第４図はバンドエリミネ
ーションフィルタの最低限の構成を示す図である。FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a diagram showing the minimum configuration of a band elimination filter.
第３図においては、音声符号／復号化装置１の雑音１を
測定するのには、スイッチｓｗｉ、ｓｗ２を実線側とし
、ディジタル正弦波発生器１０よりの正弦波を復号化器
２に入力し、復号化されたアナログ信号を、符号化器３
に入力し、符号化した第５図（Ａ）に示す如き、雑音の
重畳された正弦波のディジタル信号値（ｘ （ｔ） ＋
ｅ （ｔ） ）を、バンドエリミネーションフィルタ（
以下ＢＥＦと称す）２０にて、正弦波信号ｘ （ｔ）を
除き、第５図（Ｂ）に示す如き雑音ｅ （ｔ）のみの信
号を得、この雑音を２乗平均回路６にて２乗をとり平均
化して雑音電力を求め雑音量を測定していた。In FIG. 3, to measure the noise 1 of the speech encoder/decoder 1, the switches swi and sw2 are set to the solid line side, and the sine wave from the digital sine wave generator 10 is input to the decoder 2. , the decoded analog signal is sent to the encoder 3
The noise-superimposed sine wave digital signal value (x (t) +
e (t) ) with a band elimination filter (
(hereinafter referred to as BEF) 20, the sine wave signal x (t) is removed, and a signal containing only the noise e (t) as shown in FIG. The amount of noise was measured by taking the power and averaging it to obtain the noise power.
しかしながら、ＢＥＦの最低限の演算量は加算が４回９
乗算が５回必要で、最低限の回路構成を示すと第４図の
如くなる。However, the minimum amount of calculation for BEF is 4 additions, 9
Five multiplications are required, and the minimum circuit configuration is shown in FIG.
即ち、単位遅延素子２１〜２４が４個、回路規模の大き
い乗算器２５〜２９が５個、加算器３０〜３３が４個必
要となり回路規模が大きい。That is, four unit delay elements 21 to 24, five large multipliers 25 to 29, and four adders 30 to 33 are required, resulting in a large circuit scale.
従って、雑音量測定装置としては回路規模が大きくなる
問題点がある。Therefore, as a noise amount measuring device, there is a problem that the circuit scale becomes large.
上記問題点は、第１図の本発明の原理ブロック図に示す
如く、音声符号／復号化装置ｌにおいて、復号化器２に
ディジタル正弦波を入力し、復号化されたアナログ信号
を、符号化器３に入力し、符号化したディジタル信号を
演算処理して、雑音量を測定するに際し、
該符号化したディジタル信号の値と、この値を、入力し
た正弦波の１／２周期遅延させる手段４にて遅延させた
値とを加算器５にて加算し、その結果を２乗平均手段６
にて２乗平均することにより雑音量を測定するようにし
た本発明の雑音量測定装置により解決される。As shown in the principle block diagram of the present invention in FIG. When measuring the amount of noise by calculating the encoded digital signal input to the device 3, the value of the encoded digital signal and means for delaying this value by 1/2 cycle of the input sine wave. The value delayed in step 4 is added in adder 5, and the result is added to mean square means 6.
This problem can be solved by the noise amount measuring device of the present invention, which measures the noise amount by taking the root mean square of .
本発明は、正弦波の値と、該正弦波を１／２周期遅延さ
せた値とを加算すると０になる点に着目し、雑音量を測
定する場合の符号化器３の出力の、雑音を重畳した正弦
波の値と、１／２周期遅延させる手段４にて該正弦波の
値を１／２周期遅延させた値とを加算し、雑音のみを抽
出し、これの２乗平均をとることにより雑音量を測定す
るようにしている。The present invention focuses on the point that adding the value of a sine wave and the value obtained by delaying the sine wave by 1/2 period becomes 0, and the noise of the output of the encoder 3 when measuring the amount of noise. The value of the sine wave superimposed on the sine wave and the value obtained by delaying the value of the sine wave by 1/2 period by the 1/2 period delaying means 4 are added, only the noise is extracted, and the root mean square of the sine wave is added. The amount of noise is measured by taking the following values.
従って、正弦波を取り除くのには、１／２周期遅延させ
る手段４及び加算器５のみがあればよく、小様模な雑音
量測定装置が得られる。Therefore, in order to remove the sine wave, only the 1/2 period delaying means 4 and the adder 5 are required, and a small noise amount measuring device can be obtained.
以下本発明の１実施例に付き図に従って説明する。 An embodiment of the present invention will be described below with reference to the accompanying drawings.
第２図は本発明の実施例のブロック図である。FIG. 2 is a block diagram of an embodiment of the invention.
第２図において、第３図の場合と異なる点は、ＢＥＦ２
０の代わりに遅延素子１１〜１４及び加算器５を設け、
又１／２回路７を追加した点であるので、この異なる点
を中心に以下説明する。In Fig. 2, the difference from Fig. 3 is that BEF2
0, delay elements 11 to 14 and an adder 5 are provided,
Also, since the 1/2 circuit 7 is added, the following explanation will focus on this different point.
第２図では、ディジタル正弦波はｌＫＨ２，サンプリン
グ周波数は８ＫＨｚの場合の例を示している。FIG. 2 shows an example in which the digital sine wave is 1KH2 and the sampling frequency is 8KHz.
この場合は、１’ Ｋ Ｈｚの正弦波を１／２周期遅延
させるのには、ｌサンプル分の遅延を与える単位遅延素
子が４個必要となるので、１／２周期遅延させる手段と
して単位遅延素子１１〜１４を設けている。In this case, in order to delay a 1' KHz sine wave by 1/2 period, four unit delay elements giving a delay of l samples are required. Elements 11 to 14 are provided.
このようにすると、符号化器３の出力である、第５図（
Ｃ）に示す如き、雑音が重畳された正弦波の値と、１／
２周期遅れた値である、例えばａ。In this way, the output of the encoder 3, as shown in FIG.
As shown in C), the value of the sine wave with superimposed noise and 1/
For example, a, which is a value delayed by two periods.
点とｂ点との値が加算器５にて加算され、正弦波は打ち
消され第５図（Ｄ）に示す如く雑音のみとなり、この雑
音が２乗平均回路６にて、２乗平均 、がとられ、１／
２回路７にて１／２とされる。The values at point and point b are added in an adder 5, and the sine wave is canceled out, leaving only noise as shown in FIG. taken, 1/
The voltage is reduced to 1/2 by the two circuits 7.
これを式！示すと以下に説明する如くなる。This is the formula! When shown, it becomes as explained below.
加算器５にて加算された値Ａは次の（１）式で示す如く
なる。The value A added by the adder 5 is as shown in the following equation (1).
Ａ ＝Ｘｙｌ−ａ ＋ｅｎ−ｓ ＋ＸＲ＋ｅｒｌ ＝ｅ
ｎ−ａ ＋ｅｎ ” ” （１）但しＸ ｎ−ＩＩ
＋ Ｘ ｎは夫々ａ、ｂ点の正弦波の値で、Ｘ、、 ＝
−Ｘ Ｉ、であり、又ｅｎ−ａ ＋ ｅ ｎは夫々ａ、
ｂ点の雑音の値である。A =Xyl-a +en-s +XR+erl =e
na + en ” ” (1) However, X n-II
+X n are the values of the sine wave at points a and b, respectively, and
-X I, and en-a + e n are respectively a,
This is the noise value at point b.
（１）弐を２乗すると次の（２）式となる。(1) When 2 is squared, the following equation (2) is obtained.
八２ｓ ｅ ｎ−ａ ”＋ｅ 、、”＋２８ｆ
ｉ−ａ ’ ｅ ｎ ” ” （２）雑音の
自己相関は０となるので、（２）式の３項は平均すると
Ｏとなるので、（２）式を２乗平均すると次の（３）式
となる。82s e na ”+e,,”+28f
i-a' e n ” ” (2) Since the autocorrelation of noise is 0, the third term in equation (2) becomes O when averaged, so if we average the squares of equation (2), we get the following (3). The formula becomes
Ａ２８２ｅワ′・・・・（３）
この（３）式を１／２回路７にて１／２とすると雑音電
力ｅ ｆｉ２が求められる。A282e Wa' (3) If this equation (3) is halved by the 1/2 circuit 7, the noise power e fi2 can be obtained.
即ち、第２図の場合の、第３図のＢＥＦ２０に相当する
回路は、遅延素子４個と加算器１個で、第２図の場合は
１／２回路７が追加されても、回路規模は非常に小さく
なる。That is, in the case of Fig. 2, the circuit corresponding to the BEF20 in Fig. 3 has four delay elements and one adder, and in the case of Fig. 2, even if the 1/2 circuit 7 is added, the circuit size is still small. becomes very small.
以上詳細に説明せる如く本発明によれば、雑音量測定装
置の回路規模を従来に比し非常に小さく出来る効果があ
る。As explained in detail above, according to the present invention, there is an effect that the circuit scale of the noise amount measuring device can be made much smaller than the conventional one.
第１°図は本発明の原理ブロック図、
第２図は本発明の実施例のブロック図、第３図は従来例
のブロック図、・・
第４図はバンドエリミネーションフィルタの最低限の構
成を示す図、
第５図はディジタル正弦波と雑音量の関係を示す図であ
る。
２は復号化器、
３は符号化器、
４は１／２周期遅延させる手段、
５．３０〜３３は加算器、
６は２乗平均手段、２乗平均回路、
７は１／２回路、
１０はディジタル正弦波発生器、
１１〜１４．２１〜２４は単位遅延素子、２０はバンド
エリミネーションフィルタ、２５〜２９は乗算器を示す
。Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a block diagram of a conventional example, etc. Figure 4 is the minimum configuration of a band elimination filter. FIG. 5 is a diagram showing the relationship between a digital sine wave and the amount of noise. 2 is a decoder, 3 is an encoder, 4 is means for delaying 1/2 period, 5.30 to 33 are adders, 6 is mean square means, mean square circuit, 7 is 1/2 circuit, 10 is a digital sine wave generator; 11 to 14; 21 to 24 are unit delay elements; 20 is a band elimination filter; and 25 to 29 are multipliers.
Claims (1)
にディジタル正弦波を入力し、復号化されたアナログ信
号を、符号化器（３）に入力し、符号化したディジタル
信号を演算処理して、雑音量を測定するに際し、 該符号化したディジタル信号の値と、この値を、入力し
た正弦波の１／２周期遅延させる手段（４）にて遅延さ
せた値とを加算器（５）にて加算し、その結果を２乗平
均手段（６）にて２乗平均して測定するようにしたこと
を特徴とする雑音量測定装置。[Claims] In a speech encoding/decoding device (1), a decoder (2)
A digital sine wave is input to the encoder (3), the decoded analog signal is input to the encoder (3), and the encoded digital signal is subjected to arithmetic processing to measure the amount of noise. and the value delayed by means (4) for delaying this value by a half period of the input sine wave, are added in an adder (5), and the result is added to the root mean square means (6). ) A noise amount measuring device characterized in that the noise amount measurement device measures the square mean of the noise amount.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP70587A JPS63169123A (en) | 1987-01-06 | 1987-01-06 | Noise level measuring instrument |
| GB8730146A GB2199668B (en) | 1986-12-27 | 1987-12-24 | Connector for a camera |
| DE19873744342 DE3744342A1 (en) | 1986-12-27 | 1987-12-28 | CONTACT CONNECTION DESIGN FOR A CAMERA |
| US07/221,614 US4970558A (en) | 1986-12-27 | 1988-07-20 | Connector for a camera |
| US07/271,363 US4853725A (en) | 1986-12-27 | 1988-11-14 | Connector for a camera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP70587A JPS63169123A (en) | 1987-01-06 | 1987-01-06 | Noise level measuring instrument |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63169123A true JPS63169123A (en) | 1988-07-13 |
Family
ID=11481183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP70587A Pending JPS63169123A (en) | 1986-12-27 | 1987-01-06 | Noise level measuring instrument |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63169123A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633416B2 (en) | 2007-03-29 | 2009-12-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit capable of screening conforming digital-analog converters and analog-digital converters to be mounted by auto-correlation arithmetic operation |
-
1987
- 1987-01-06 JP JP70587A patent/JPS63169123A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633416B2 (en) | 2007-03-29 | 2009-12-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit capable of screening conforming digital-analog converters and analog-digital converters to be mounted by auto-correlation arithmetic operation |
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