JPH0365048B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a digital signal processing device.

Differential filtering and smoothing operations of digital signals are one of the basic calculation processes in fields such as automatic waveform measurement and digital image processing.
Multiplication and division processing is generally required in digital filtering processing of discrete time-series signals. For example, in order to realize the above filter using software on a minicomputer or microcomputer and obtain good low frequency characteristics, it is necessary to calculate coefficients of decimal point data, which require precision, and to repeatedly calculate their multiplication and division. needed,
There was a problem that the processing time was long and it was difficult to put it into practical use. On the other hand, even when the above filter is implemented in hardware, a multiplication/division circuit is required, resulting in a complicated circuit configuration, and furthermore, there is a drawback that the calculation speed of the filter is affected by the length of data.

Furthermore, when both the smoothing operation and the differential operation are implemented using software, different software configurations are required, which occupies memory and reduces software execution efficiency. Furthermore, if both of the above operations are implemented using hardware, two different circuit configurations are required, which has the disadvantage of increasing the number of elements.

Furthermore, broadband noise is usually superimposed on the above-mentioned time-series signals, and filtering thereof, especially multi-stage (high-order) filtering, has been considered difficult.

An object of the present invention is to provide two functions of high-speed digital differentiation and smoothing processing in the same structure, which can be configured using simpler means than the conventional signal processing method related to differential filtering smoothing, and which also has good low-frequency characteristics. The object of the present invention is to provide a signal processing device that can be realized using the following methods.

According to the present invention, a digital signal sampled in a time series is delayed, and a second and a third signal, which are equally spaced before and after the first signal, are generated in the time series.
a delay means for outputting a predetermined number of pairs of signals, the first signal and 0 or 1;
a first multiplier that multiplies the second signal by a first coefficient signal that takes a value of +1 or -1; and a second multiplier that multiplies the second signal by a second coefficient signal that takes a value of +1 or -1. , a first addition means for adding the third signal and the output of the second multiplication means, corresponding to a time interval between the output of the first addition means and the second or third signal. a predetermined number of basic circuits each having a third multiplication means for multiplying by a second coefficient signal taking a value of 0 or 1; and a second addition for adding the outputs of these basic circuits. and a third addition means for adding the output of the first multiplication means and the output of the second addition means, and the low-frequency differential characteristic and the smoothing characteristic can be realized with the same configuration. A signal processing device is obtained.

Next, the present invention will be explained in detail. The ideal frequency characteristic in low-frequency differential processing is given by equation (1).

H〓 ⁽¹⁾ (ω)=jω |ω|≦απ 0 απ<|ω|<π (1) Here, απ (0<α<1) indicates the cutoff frequency, and the sampling period is assumed to be T=1. are doing.

This frequency characteristic is shown in FIG. When the characteristic expressed by equation (1) is approximated by an acyclic symmetric FIR filter, its frequency characteristic is given by equation (2).

F ⁽¹⁾ (ω)=j _P 〓 ⁿ⁼¹ _o sinω (2) Expressing equation (2) in the time domain, the output signal sequence y _k ⁽¹⁾ of first-order differential filtering is It is expressed as a linear sum of central differences of the input signal sequence x _k .

y _k ⁽¹⁾ = d/2 _P 〓 ⁿ⁼¹ h _o (x _k+o −x _ko ) (3) where h _h = d・_ho , d=1/ _P 〓 ⁿ⁼¹ (n・h _o )T
shows. In equation (3), d is a scale factor (constant) and is unrelated to the difference calculation in equation (3), so there is no need to take it into account in actual calculation.
Furthermore, in equation (3), if _ho is set to "0" or "1", equation (3) shows that the first-order differential characteristic can be realized only by difference calculation.

Next, the frequency characteristics in smoothing processing are expressed by equation (4).

F ^(m) (ω)=h ₀ ^(m) +2 _P 〓 ⁿ⁼¹ _o ^(m) cos (nω) (4) Expressing equation (4) in the time domain, the smoothing processing output signal
As shown in Equation (5), y _k ^(m) is expressed as a linear sum of the input signal sequence x _k- and a temporally symmetric signal sequence centered on x _k .

y ^(m) _k = h ₀ ^(m) x _k + _P 〓 ⁿ⁼¹ h _o ^(m) (x _k+o + x _ko ) (5) where h _(o) ^(m) = d・h _o ^{( m)} , d=1/ _P 〓 ^n=-P _ho ^(m) . In equation (5), d is a scale factor (constant), and if h _o ^(m) is “0” or “1”, equation (5) can achieve smooth characteristics with only a simple linear sum. It shows.

Here, if we pay attention to the difference term (x _k+o −x _ko ) in equation (3), the linear sum term (x _k+o + x _ko ) in equation (5) is the second term in equation (3). This corresponds to converting the sign of the time series signal x _ko . This shows that the smoothing operation based on equation (5) can be achieved by substituting the subtraction and addition operations among the differential operations expressed in equation (3) and adding the term corresponding to h ₀ . . FIG. 2 shows a configuration in which the selection between the subtraction operation and the addition operation can be switched and selected by an external signal. By connecting an addition device and a signal delay device to the configuration shown in FIG. 2, a signal processing device that can be used in conjunction with the differentiation and smoothing processing shown in equations (3) and (5) can be realized.

This signal processing device is generally expressed by equation (6) using equation (3) and equation (5).

y _k = h ₀ x _k + _P 〓 ⁿ⁼¹ h _o (x _k+o + j・x _ko ) (6) Here, h _o h ₀ = 0 or 1 j = ±1 Based on the above principle, FIG. 3 shows an example in which p=4 in equation (6). In FIG. 3, a signal delay device (shift register) 1 outputs a signal obtained by delaying a time-series digital signal by a predetermined time according to a clock. To explain the operation, the signal at time k-n output from the signal delay device 1 depends on the clock signal CK.
x _ko is input to exclusive logic unit 2 .

On the other hand, by inputting the signal J to the exclusive logic operation device 2, an addition or subtraction operation between the signal x _k+o at time k+n and the signal x _ko is determined. In other words, the differential characteristic or the smoothing characteristic is selected depending on the J signal. In the adder 3, the output signal from the exclusive logic operation device 2 and the output signal from the signal delay device 1 are added, and in the AND operation device 4, the output signal is ANDed with the coefficient _ho (“0” or “1”). An operation is performed.

The adders 5, 6, and 7 repeatedly perform an operation on the output signal from the AND operation device 4, which corresponds to the linear sum of the second term in equation (6). Here, two signals outputted from the shift register and located at temporally symmetrical positions are input to each input terminal 5a, 5b, 6a, and 6b. The adder 8 receives a signal obtained by multiplying the signal x _k corresponding to time k by a coefficient h ₀ .
This addition device is necessary when smoothing characteristics are required in this signal processing method.

The output signal _yk thus added by the adder 8 becomes a differential filtering output or a smoothing filtering output signal.

As described above, according to the present invention, the following effects can be obtained compared to the conventional system. (1) Compared to known digital filters, this method does not require multiplication/division calculation processing, so high-speed signal processing is possible, and filtering output can be obtained almost in real time. . (2) Since this method consists only of addition/subtraction and logical operations, it can be easily integrated into an integrated circuit.
(3) Differentiation and smoothing of time-series signals can be processed with the same configuration. (4) Since the same component can be used as a differential filter and a smoothing filter just by specifying parameters from the outside, it is possible to reduce the number of elements in the entire signal processing device. (5) By appropriately selecting the coefficients, differential filters and smoothing filters with a wide variety of characteristics can be realized with the same configuration. (6) When increasing the number of bits of the time-series signal to be processed, this can be achieved by connecting this method in parallel. Furthermore, there is no delay in calculation speed due to an increase in data length.

[Brief explanation of drawings]

Figure 1 shows the ideal low-frequency differential frequency characteristics, Figure 2
3 is a diagram showing an example of a configuration in which a subtraction operation and an addition operation can be selected by switching using an external signal, and FIG. 3 is a diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1 A predetermined number of pairs of signals are obtained by delaying a digital signal sampled in time series and forming a pair of second and third signals that are equally spaced in time series with the first signal as the center. a delay means for outputting the first signal; a first signal having a value of 0 or 1;
a first multiplication means for multiplying the coefficient signal by the second signal, a second multiplication means for multiplying the second signal by a second coefficient signal having a value of +1 or -1,
a first addition means for adding the signal of 0 and the output of the second multiplication means; A predetermined number of basic circuits each having a third multiplication means for multiplying by a second coefficient signal having a value of 1 are provided, and a second addition means for adding the outputs of these basic circuits; a third addition means for adding the output of the first multiplication means and the output of the second addition means;
1. A signal processing device that selectively performs either differentiation processing or smoothing processing of the digital signal according to the value of a coefficient signal.