JPS63169068A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly, but not exclusively, to insulated gate field effect transistors.

Various semiconductor fabrication methods include providing a conductive layer on the surface of a semiconductor, where the conductive layer is formed with at least one opening, and insulating material being grown on the surface to cover the conductive layer. Are known. As far as the manufacture of insulated gate field effect transistors is concerned, known methods include providing a conductive gate in an insulating layer on one surface of a semiconductor to form an insulated gate structure having a gate region with an opening therein. introducing impurities into the semiconductor to form a source region of one conductivity type aligned with the insulated gate structure and a channel of the opposite conductivity type below the gate region;
An insulating material is grown on the surface to cover the insulated gate structure.

One such method for manufacturing insulated gate field effect transistors (hereinafter referred to as IGFETs) is described in the 1984 IEDI Proceedings No. 447.
- Mr. H. Esaki (H, Bsaki) and O. Ishikawa (0.1 Shikawa) on page 450.
900! , lHz 100! AVD-MO3FET
With Silicide Gate Self-Aligned
Channel <A 9001Hz100W VD-MOS
FET with silicide gate se
lf-aligned channel) J.

The IGFET described in the said paper is of DMOS type, i.e. the channel length within the device is precisely determined by double lateral diffusion of different impurities using the gate layer as a mask, as described. It is formed. The IGFET is also vertical, interdigitated, with its source and drain electrodes on opposite major surfaces of the semiconductor.
erdigitated) has a 7-sugate structure. As described in the aforementioned paper, the central portion of each gate finger of the comb source-gate structure reduces the drain-to-gate capacitance to 900 M as mentioned in that paper.
removed to allow high power gains at relatively high frequencies of Hz.

European Patent A 67475 similarly describes a vertical DMS run lister (DMO3T) in which the central part of the gate finger is either removed or made of a higher resistivity material than the edge of the gate finger in order to reduce the gate drain capacitance. Are listed. As described in the aforementioned European patent, the gate fingers are formed of relatively high resistivity polycrystalline silicon, with a layer of doping elements forming strips of higher conductivity along the edges of the gate fingers. diffused laterally within the margins of the. The more resistive polycrystalline silicon portion in the center of each gate finger can be left in place or removed with a suitable etching technique.

In one aspect of the invention, the opening is made small enough that the insulating material grown on the edges of the conductive layer bounding the opening meets and blocks said opening, and the growth of insulating material is prevented. etching the insulating material anisotropically towards said surface for a sufficiently long period of time to expose the conductive layer and/or a portion of the semiconductor surface larger than the opening and not covered by the conductive layer; A window is formed in the insulating material covering the conductive layer, and an anisotropic etching leaves the insulating material at the edges of the conductive layer so that the opening remains closed.

As used herein, the term growing includes all methods of providing insulating material to a surface;
It is therefore likely to be understood to also include, for example, the deposition of insulating material onto a surface.

Although it is possible to provide a conductive layer directly on the semiconductor surface, for example to form a Schottky contact with the surface,
An insulating layer can also be provided between the surface and the conductive layer.

a conductive layer, with at least one opening in an area of the conductive layer larger than the opening and bounded by one or more areas of the semiconductor surface not covered by the conductive layer; may be formed and anisotropically etched to form the window or windows in the insulating material covering the region or regions. A conductive layer may be formed with a plurality of said openings and divided into a plurality of regions by a portion of the semiconductor surface larger than the openings, each region having at least one of the openings.

Each region of the conductive layer can be formed with multiple openings. In either case, the anisotropic etching opens one or more windows in the insulating material covering the one or each area, but the one or each opening is closed or covered with insulating material. It remains as it is.

Thus, by using the method of the invention, the opening is small enough and the insulating material grown on the edges of the conductive layer bounding the opening meets and covers or closes said opening. The growth continues for a sufficiently long time that the insulating material remains covering or at least partially filling the opening in the conductive layer after the anisotropic etching step. If the growth of the insulating material is substantially isotropic, growth should continue until the insulating material forms a layer having a thickness equal to at least half the width of the opening. Such methods can be applied to manufacturing various types of semiconductor devices. In particular, the use of the method according to the invention provides a simple way to passivate semiconductor surfaces within openings. Furthermore, if the opening divides the conductive layer into separate conductive regions, the method according to the invention facilitates isolation of the conductive regions from each other while allowing individual electrical connections to the conductive regions. It can be used for.

As can be seen, the formation of an opening in the conductive layer means that there is a step, usually at the top surface of the semiconductor device, at each transition from the edge of the conductive layer to the semiconductor surface. Such a step is undesirable, especially if the metallization is provided on the top surface, since said step can create weak points in the metallization. By using the method according to the invention, the insulating material is anisotropic in order to expose the conductive layer and/or form a window over an area of the surface of the semiconductor that is not covered by the conductive layer and is larger than the opening. The insulating material remains in the opening even after being etched. Accordingly, the steps of the top surface are reduced and smoothed, if not completely eliminated, so that the top surface extending over the opening is not even at least partially filled with insulating material. It is flatter than the case, thus reducing the possibility of weak points in the metallization subsequently provided to contact the conductive layer and/or semiconductor surface overlying the top surface.

As previously mentioned, the windows are formed through anisotropic etching. The window typically (but not necessarily) extends well through the insulating material to expose the semiconductor surface, but in any case the window allows impurities to be introduced into the semiconductor. The insulating material remaining at the edge of the conductive layer bordering said portion forms at least part of the window, and the insulating material remaining within the opening protects the underlying portion of the semiconductor from the introduced impurities. cover This ensures that a region of a given conductivity type is formed in the semiconductor, aligned with the edges of the conductive layer bounding said portion, without introducing undesired impurities into the semiconductor below the opening. enable.

Moreover, the surfaces exposed by anisotropic etching can be further processed in another manner without fear of contaminating the semiconductor beneath the opening, unless further processing attacks and removes the insulating material within the opening. can do. For example, metals can be deposited on surfaces exposed by anisotropic etching, and if these surfaces are made of silicon, super-refractory metals can be deposited to self-locate onto the exposed silicon surfaces. form a combined super heat-resistant metal silicide,
Thus, the resistivity of the exposed surface can be reduced.

The method according to the invention can be carried out using e.g. a charge-coupled device or an IGF.
It can be used in the production of ET.

In another aspect of the invention, the invention provides a method of manufacturing an IGFET, the method comprising providing a conductive gate layer on a surface of a semiconductor having an opening therein and a conductive gate region. forming an insulated gate structure and introducing impurities into the semiconductor to form a source region of one conductivity type aligned with the insulated gate structure and a channel region of the opposite conductivity type underlying the gate region; A method of manufacturing an insulated gate field effect transistor in which an insulating material is grown over an insulated gate structure, wherein the insulating material grown on the edge of a conductive gate layer bounding an opening meets and closes the opening. The opening in the gate region is made small enough and the growth of the insulating material is continued for a long enough period of time to ensure that the insulating material remains at the edges of the insulated gate structure and is formed within the insulating material by anisotropic etching. An insulating material is anisotropically etched toward the surface of the semiconductor to bound at least a portion of the window and fill the opening in the gate region, and impurities are introduced to form the source and channel regions through the window. It is characterized by forming.

Using this method, insulating material can be left in the opening in the gate to provide passivation of the surface.

The insulating material left on the sides of the insulated gate structure to form at least part of the window also serves to enable alignment of the source and channel regions with the insulated gate structure, while the insulating material remaining in the frontage The material prevents the surface beneath the opening from becoming contaminated with impurities. Therefore, an rGFET with a hollow gate structure can be formed without the need for a final step of removing the central portion of the gate region.

Moreover, since the openings in the gate region can be formed in the same process at the same time as the gate region boundaries, tolerance issues are minimized, allowing for more precise alignment of the source and channel regions versus hollow gate structures. Allow alignment.

A window in the insulating material typically extends just through the insulating material to expose the semiconductor beneath the window. However, the impurities to form the source and channel regions just form a window in the thin insulating material that is thin enough to allow implantation of the desired impurity without extending through the insulating material. It can also be injected later.

In one embodiment of the invention, the source region is formed in a semiconductor region of opposite conductivity type, such that a portion of this semiconductor region provides a channel region, and a masking region and a window are provided between the masking region or the insulating region. The semiconductor region is sourced with one or more masking regions extending across the window formed by anisotropic etching to form one or more exposed portions of the source region not covered with material. shorting the region, etching away the exposed portion of the source region to expose the underlying portion or portion of the semiconductor region, and removing the masking region;
Metallization is provided within the window to short the exposed portion of the semiconductor region to the source region.

The window may be elongated and provided such that one or each masking area extends completely across the width of said window or only partially across the length of the window.

Therefore, the windows used to introduce the source and channel regions can be used to short the semiconductor region to the source region, in which case the insulating material remaining at the edges of the insulated gate structure It is insulated from the source region to prevent accidental short circuits between the source region and the gate. Such an arrangement allows both the same window to be used to introduce the impurity and to short the source region to the semiconductor, and the exposed portion of the semiconductor region to be automatically aligned with the window. Alignment problems can be reduced for this reason, thus eliminating or at least mitigating the alignment problems of the previously mentioned known methods, allowing the production of devices with more reproducible properties.

If the window is elongated, the masking area is provided on the insulating layer so as to extend completely across the window in a direction transverse to the length of said window. Generally, the masking step provides a plurality of spaced apart masking regions generally parallel to each other extending across the window to form a plurality of spaced apart exposed regions of the source region within the window. It consists of many things. Typically, each masking area extending over the window is evenly spaced along the length of the window.

The masking area may be formed by regularly spaced holes formed in the masking layer, in which case the width of the holes is greater than the width of the window, or by an IJ knob or other suitable arrangement across the window. However, it is only necessary that, in the direction across the window, the dimensions of the masking area and the spacing between them are such that the masking, even taking into account possible misalignment tolerances, It is only necessary to ensure that the masking area is sufficient to ensure that it extends completely across the window where it is needed and does not extend across the window where masking is not required. be. A strip-like masking area extending across the window, in the preferred arrangement perpendicular to the window, will prove particularly advantageous, since there is no significant lateral misalignment between the masking area and the window. This is because alignment does not affect the positioning of the exposed portion.

The method further includes etching to expose the underlying portion of the semiconductor region and prior to removal of the masking region to increase surface doping of the exposed semiconductor region prior to providing the source metallization in the window. , another impurity of opposite conductivity type can be introduced through the window.

The conductive layer is provided such that the conductive region is elongated and the opening extends along the length of the conductive region to form two conductive region strips, and an anisotropic etching of the insulating material is performed in the gate region. impurities are introduced into the semiconductor to form a respective source region aligned with each long edge of the gate region and a respective channel region below each gate region strip. can. If the semiconductor device is an IGFET, the conductive gate region may form a single cell of the IGFET with two adjacent source regions, an underlying channel portion, and an associated drain region. An IGFET may consist of a number of such cells having one common drain region provided adjacent to the surface of the semiconductor opposite to said surface. In such an arrangement, the gate layer consists of spaced apart elongated gate regions connected to each other by transversely extending conductive strips provided with a conductive layer, so that after anisotropic etching , the insulating material remaining at the edges of the conductive layer forms windows for introducing impurities to form the source region and channel region, where each window consists of two adjacent gate regions and two adjacent conductive regions. The electrical strip may be bounded by insulating material left on opposite edges of the strip.

Depending on how the insulating material is grown, anisotropic etching may expose the surface of the conductive layer. For example, if the semiconductor is made of silicon and at least the top surface of the gate layer is made of polycrystalline silicon, a metal is deposited on the exposed surface by anisotropic etching, and then a super refractory metal is deposited on the exposed surface. , can be annealed to form a self-aligned super refractory silicide over the exposed portions of the gate and source regions. If the source region is shorted to the underlying semiconductor region as described above, the conductive gate layer may be protected with an etch-resistant layer, such as a silicon nitride layer, during the etching step that exposes the p-type semiconductor region. is normal. The silicon nitride layer and any other insulating layers may then be removed and the conductive layer may be exposed for silicidation after etching to expose portions of the semiconductor region.

This silicidation can be provided in addition to or instead of another doping of the exposed semiconductor region.

Of course, the window need not necessarily expose the surface of the semiconductor, and the anisotropic etching may only result in the gate layer surface being exposed for silicide. Alternatively, if the gate is a polycrystalline silicon gate formed on a silicon body, the insulating material results in a thick insulating material over the gate such that only the semiconductor portion within the window is exposed for silicidation. Methods such as wet oxidation
idation).

In EP A 54 259, an insulating material covering the surface of a silicon body supporting an insulated polycrystalline silicon gate is anisotropically etched to form a surface field oxide (FIE).
A lateral (
It is noteworthy that a method for fabricating an IGF[ET, i.e. having source and drain regions adjacent to the same side of the semiconductor] is described. The super-refractory metal is deposited on the exposed surface by anisotropic etching (which may or may not include the gate) to form a metal layer or super-refractory metal silicide self-aligned to the gate. .

In order that the invention may be more easily understood, it will be described by way of example with reference to the accompanying drawings.

The drawings are not to scale, and the dimensions of each part are shown enlarged or reduced for clarity.

FIGS. 2 and 3 show IG produced by the method of the present invention.
A part of the FET is shown.

The IGFIET shown in FIGS. 2 and 3 above is a vertical D type having a comb-shaped structure suitable for use at high frequencies, e.g. UHF frequencies, typically in the I GHz range.
MO3) Run lister. In this DMO3T, as shown in FIG. 2, the semiconductor 1 of the DMO3T is
It has a source region 2 and a drain region 3 disposed on each of the two opposing main surfaces 4 and 5, so that during operation of the device current flows between the two opposing main surfaces 4 and 5, so that the vertical be regarded.

The gate layer 6 of the IGFET has regularly arranged openings 7.
This opening is rectangular as shown in the figure and has a conductive strip extending laterally (IJ tube or busbar 9).
forming parallel spaced rectangular gate fingers or regions 8 connected by. Each gate finger 8 is formed with a central rectangular opening 10 extending along the length of the gate finger 8 and dividing the gate finger into two gate finger strips 8a. Therefore, ff19a of the generatrix 9 in the relationship extending in the transverse direction
Together, the outer edge 8'a of the gate finger 8a forms an opening 7, while the inner edge ff1 of the gate finger strip
Ba forms the opening 10.

Although a rectangular geometry is shown for gate layer 6, it will be appreciated that other suitable geometries may be used depending on the desired source region shape.

In the arrangement shown in FIGS. 2 and 3, a number of source regions 2 are provided adjacent to the main surface 4, while only one drain region 3 is provided in common to all source regions 2 on the main surface 4. It is located adjacent to.

As previously mentioned, IGFETs are DM[lST, i.e., the channel length is precisely formed by double lateral diffusion of different impurities in the semiconductor. Therefore, by introducing impurities into the gate layer through the opening 7, this gate layer can be used as a mask, as will be explained later.
Each source region 2 is formed in a respective semiconductor region 12 of opposite conductivity type, so that the boundary of each source region 2 is aligned with the edge of the associated opening, and parts of the associated semiconductor region are formed in the same two finger strips 8a. A respective channel portion 13 is formed under a respective gate finger strip 8a extending between a respective source region 2 and a respective drain region 3. As can be seen in particular from FIGS. 1C and 2, each source region 2 is associated with two channel portions 13 and thus with two gate fingers 8.

The source regions, e.g. source regions 2' and 2' in FIG. 2, together with the gate finger 8 and the underlying channel portion 13 disposed between these two source regions form one cell of the IGFET and thus the device. Apart from the periphery of the active part of , each source region 2 is common to two cells. Typically, IGF[ET has several hundred such cells. Although the cell is shown as rectangular in shape, it will be appreciated that any suitable geometry may be used.

As will be described in detail later, the portion 12a of the semiconductor region 12
An opening 2a is provided in the source region 2 to expose the source region 2, each source region being shortened to the associated channel region by a later applied source metallization.

An embodiment of the invention for manufacturing the IGFET shown in FIGS. 2 and 3 will now be described, further features of which will become apparent from the following description.

The semiconductor has an n' conductivity type single crystal silicon substrate 14 on which a higher resistivity n type single crystal silicon layer 15 is epitaxially grown. This substrate typically has 10
-3 ohm cm and a thickness of 250 micrometers, while the epitaxial layer can have a resistivity of 1 ohm cm and a thickness of 8 micrometers.

An oxide layer 16 (FIG. 1a), typically 0.07 micrometers thick, is grown on the surface 4 of layer 15 by conventional thermal techniques, and then a gate layer 6 is grown on said oxide layer 16. will be deposited. In this particular embodiment, gate layer 6
has a composite layer structure. Therefore, a polycrystalline silicon layer 61 is deposited on the oxide layer 15 and an insulating layer 62
A layer of silicon dioxide, for example, follows, and then an etch-resistant layer 63 of silicon nitride, for example, is deposited. Using conventional masking and etching techniques, unnecessary portions of composite gate layer 6 are removed to form hollow gate fingers 8 interconnected by busbars 9 (FIGS. 2 and 3).
figure).

In order to obtain the required low resistivity, the polysilicon gate layer 61 is doped, for example with boron or phosphorus. Said gate layer 61 can be deposited as a doped layer, but this doping can also take place after the deposition and patterning of the gate layer 6. The doping of the gate layer 6 may be carried out, for example, during the formation of the source region 2 and the semiconductor region 12, or by doping the exposed edges of the gate layer in a patterned manner as described in EP A 67 475. It may also be a lateral diffusion of boron, for example. In the latter case, the openings 10 in the gate fingers 8 are typically (but not necessarily) formed after doping of the patterned gate layer 6 as described in the aforementioned European patent.

It will be appreciated that the gate layer 61 need not necessarily be a polycrystalline silicon layer, but may be any suitable conductive layer such as a super refractory metal layer deposited on the oxide layer 16, a super refractory metal silicide layer (e.g. a platinum silicide layer) or a composite of two or more of the aforementioned materials.

After the gate layer 6 has been formed, an insulating material 16', for example silicon dioxide, is deposited on the main surface 4 by a suitable vapor deposition technique.

The insulating material is grown on all exposed surfaces, namely the main surface 4 (if exposed), the surface 63' of the gate layer and the edges 9a, 3'a of the gate layer 16 and directly over them.

Two gate finger strips 8 for each gate finger
The spacing of a is small enough and the period during which the insulating material is deposited is long enough that it grows laterally (i.e. across the main surface 4) of the elongated gate finger 8 on the inner edge 8''a of the gate finger strip 8a. The insulating material meets or melts to completely cover the opening 10.

The meeting or penetration of the insulating material grown on the edge 8'λ depends not only on the spacing of the inner edge [a of the gate finger 8, that is, the width of the opening 10, but also on the width of the insulating material grown on the edge 1. It goes without saying that it depends on the thickness. The thickness of the composite gate layer 6 is comparable to the width of the opening 10 and the growth of the insulating material is substantially isotropic (i.e. the insulating material has approximately the same thickness as on the surface 63' of the gate layer). 1! 8'a and 8'S), the insulating material is grown on the sides of the edges 8'3 of the opposing gate layers so that they meet and close or cover the opening 10. must be grown long enough to have a thickness at least half the width of the opening IO. However, for practical purposes, the width of the opening 10 should be small enough so that only a moderate thickness of insulating material grown on the inner edge 8a is required to fill the opening 10. It is. This is because an insulating layer that is too thick can unduly strain the semiconductor and, as will be seen below, make the subsequent etching step more time consuming.

In the particular embodiment described, the gate fingers 8 have a width of 3 micrometers and are separated by openings 7 of the same width, while the central opening 10 within the gate fingers has a width of 1 micrometer. Therefore, two gate finger strips 8a each having a width of 1 micrometer can be formed. With such dimensions, in this case, if the growth of the insulating material were completely isotropic, the opening lO
Continuous growth to a thickness of just over 0.5 micrometers may be sufficient to ensure that the gate finger strips 8a are covered with meeting or penetrating insulating material grown on the sides of the gate finger strips 8a. However, the growth of the insulating material is not completely isotropic, for example on the surface 63' of the gate layer 6.
an upright fi9a of the gate layer 6 than above;
3'a and 8a may be smaller, so the growth was 5 micrometers thick to ensure that the opening 10 was completely covered by the laterally grown insulating material. It should be continued for a short period afterward. Figure 1b diagrammatically shows the thickness of the insulating material when growth is stopped.

When the growth of the insulating material is stopped, the insulating material is e.g.
Using a reactive ion etching technique, for example using a HF, and argon gas mixture, the main surface 4 is etched to expose the surface 4 below the opening 7 of the gate layer 6 and the surface 63' of the composite gate layer 6. It is etched in all directions. When the insulating material is attacked in a direction perpendicular to the main surface 4 by anisotropic etching, a predetermined vertical thickness of the insulating material is removed.

Thus, main surface 4 within opening 7 and surface 63 of gate layer 6
' is exposed by anisotropic etching, the fillet 17 of the initially laterally grown insulating material becomes the gate layer 6.
edges 9a, 8'a, forming respective windows 18 of insulating material above and within each opening 7. The growth of the insulating material continued such that the insulating material grown on the sides of the edges 8' of each gate finger 8 met and covered the openings 10, so that the anisotropic etching covered the openings 10.
2 of each gate finger 8, leaving a thickness of insulating material 19 extending to the level of surface 63' without exposing major surface 4 within.
A generally smooth surface is provided above between the two gate finger strips 8a. FIG. 1C diagrammatically depicts a semiconductor that has just been anisotropically etched.

Impurities are then introduced into the semiconductor through window 18 to form semiconductor region 12 and source region 2 . In one example, boron ions are implanted through window 18 using an implant dose of 10" cr2 and an energy of 150 KeV.
ant) followed by a drive-in, for example at 1050° C. for 30 minutes. Then 5
A second ion implantation step is performed through the window 18 using an energy of 0 KeV and an implantation dose of 101015a'', followed by an annealing step for example at 1000° C. for 10 minutes. Thus, the p-type semiconductor region 12 and An n-type source region 2 is formed, in which the length of the channel region is determined by the difference in the lateral diffusion lengths of the n-type and p-type dopants under the conditions mentioned above.Diffusion lengths of the dopants under the particular conditions used Knowing the thickness of the insulating material fillet 17, the thickness of the insulating material fillet 17 can be determined so that the source region 2 is at the edge 8' of the gate finger 8 as shown in FIG. 1C.
You can choose to align with a. Channel area 1
3 may be aligned with the edge of the gate finger 8, or alternatively, the IJ knobs 8a may extend laterally towards each other beyond the channel region 13 (as shown). field-brating
-plating) effect. The source right and semiconductor regions can be formed to extend to a depth of 0.5 micrometer and 1.0 micrometer below the main surface 4, respectively.

The insulating material covering the opening 11 prevents dopants from entering the semiconductor below the opening IO during the formation of the source region 2, thus providing a hollow gate structure before the formation of the source region 2 and the semiconductor region 12. enable.

As mentioned above, source region 2 and semiconductor region 12 are formed by ion implantation, but other suitable processes, such as a diffusion process, may be used if window 8 has an exposed surface.

After the formation of the source region 2 and the semiconductor region 12, a suitable resist layer 20 is then applied to the surface of the insulating material (FIG. 1d), such that the masking region 20a of this resist layer 20 completely traverses the window 18 of the insulating material. The resist layer is patterned using conventional techniques to form apertures 21 extending along the length of the resist layer.

Each window 18 has one or more masking areas 20a.
, and thus said window 18 and the associated masking region 20a together form one or more exposed regions 2a of the associated source region 2, i.e. the masking region or in which the window 18 is formed. A region 2a of the source region 2 that is not covered with the insulating material is formed. The exposed area 2a within each window 18 is thus not only affected by the masking area 20a, but also by the masking area 20a and the window 18.
formed by a combination of As can be seen, masking area 20a defines one dimension of exposed area 2a and window 18 defines the other dimension of exposed area 2a. Any desired shape may be used for the holes 21, but as shown, the holes 21 are rectangular to match the rectangular pattern adopted for the windows 18 and gate layer 6. be. The dimension or width of the hole 21 across the length of the window 18 of interest (perpendicular to the length in the illustrated embodiment) is at least twice the maximum possible misalignment error.
larger than the width of the window 18 and therefore, even taking into account possible misalignment errors, the edge 21a of the longitudinally extending hole 21 of the window 18 concerned is larger than the long edge 18a of the window.
There will be no overlap.

Instead, the resist layer 20 is formed as a series of discrete strips extending across (or perpendicular to, in the illustrated embodiment) the window 18, with the resist layer extending completely across the window. It is also possible to further reduce the possibility of overlap with the long edge of the window.

Thus, resist layer 20 covers only those portions of window 18 that are desired to be masked, and where the resist layer covers portions of window 18, it extends completely across the width of window 18. The resist layer should extend across the window and beyond both sides of the window a distance at least equal to the maximum expected tolerance.

Within window 18, the relative dimensions of exposed region 2a and unexposed source region 2b covered by resist masking region 20a may be in any desired ratio. In the arrangement shown in the figure, the resist layer has exposed regions 2a of the source region and unexposed (covered) regions 2a of the source region.
The regions 2b are chosen so that equal areas are alternately provided. It will be obvious that the exposed area 2a and the covered area 2b may have any desired shape. The number of exposed and covered areas depends on the particular device and the length of the gate fingers 8, the latter depending on the desired GRC time constant.

Exposed region 2a of the source region is then removed using a conventional etching process to expose lower region 12a of p-type semiconductor region 12. Resist layer 20 is then removed.

After the source region 2 and drain region 13 are formed and the semiconductor region 12 is exposed as described above, a super refractory metal silicide layer 11 can be formed over the exposed region of the surface 4 of the silicon body. . Gate layer 61 may also be exposed using a suitable etchant to remove silicon nitride layer 63 and insulating layer 62 for subsequent silicidation. Such an arrangement would require the provision of new insulating material over the silicide gate layer to prevent subsequent shorting to the source metallization and reduce capacitance thereto. The metal silicide layer 11 is formed by depositing a super-refractory metal such as tungsten, molybdenum, platinum or titanium onto the semiconductor in a known manner, and then forming a super-refractory metal silicide only on the exposed areas of the silicon surface. , for example by annealing thermally or with the use of a laser beam. Any metal remaining on the insulating material is removed by a suitable method, such as acid treatment.

Although the previously described method of shorting the p-type semiconductor region 12 to the source region 2 is particularly advantageous, alternative methods can also be used. Thus, for example, after implantation of impurities through the window 18 to form the p-type semiconductor region 12 and the source region 2, the portion 2a of the source region is
A subsequent p-type over-doping implantation is performed to form a p-type conductive region of the semiconductor region 12.
A suitable masking layer (similar to layer 20) may be provided over the insulating material to protect it from g implantation. Thus, after the implantation step, the surface 4 is provided with alternating source regions 2b and 128. In such a case, it is also possible to form a super refractory metal silicide before forming the source and drain regions and implant the necessary impurities through the super refractory metal silicide. Boundary mixing (interf) with the ion beam to enhance silicide formation
ace mixing) can be used. Group III or III dopants can be used as the ion beam, so that the residual silicide formation that forms the source and semiconductor regions and the doping of the underlying silicon are combined with the silicide formation on the exposed silicon surface. Can be done at the same time.

If such a method is used, the super-refractory metal silicide layer can of course be applied after, simultaneously with, or before the source region 2 and semiconductor region 12.

In an alternative arrangement, source regions 2b may be implanted through a mask similar to mask 20, providing alternating source and drain regions. However, such an arrangement naturally results in short channel lengths.

If no etching step is performed to short p-type semiconductor region 12 to source region 2, surface 61' of conductive gate layer 61 can be exposed during anisotropic etching. In fact, in such an arrangement there is no need for conductive gate layer 61 to be protected at all, and layers 62 and 63
It would probably be better without it. However, in such an arrangement, the conductive gate layer 61 is of course removed by subsequent growth of the insulating material through a suitable mask to prevent shorting to the overlying source metallization. It will have to be covered. If the upper layer of conductive gate layer 61 is formed of polycrystalline silicon, a self-aligned super refractory metal silicide can be formed on exposed surface 61'.

In the method described above, the insulating material is formed by a suitable vapor deposition technique, for example by oxidizing the silicon surface 4 and the gate layer 6, if the gate layer is made of polycrystalline silicon. be able to.

Once the semiconductor and source regions 12 and 2 and the metal silicide (if required) have been formed as described above, metallization is deposited on the surface 4 to form the source and gate metallizations. can be done. Needless to say,
If the gate layer surface 6F is exposed for silicidation purposes, the exposed silicide layer may be removed using a suitable mask before depositing the metallization to prevent the insulating material from shorting the gate and source. A gate layer is deposited onto the surface 61'. Of course, windows are formed in the insulating material to bring the metallization into contact with the busbar 9. After metallization is deposited on the insulating material to contact line 9 and short circuit p-type semiconductor region 12 to source region 2, separate source metallization 23 and busbar or gate metallization 24 are formed. For this purpose, known resist masking and etching techniques are used. The source metallization has been omitted in FIG. 3 for clarity, but of course the edge of the source metallization extending over the window 18 is shown in bold line 23a in FIG. The edge of is likewise indicated by a thick line 24a.

Source metallization 23 thus shorts the exposed p-type semiconductor region within each window 18 to exposed source region 2a.

The drain of the transistor is formed by the n-type laminate 3, and an electrode 25 is provided on the free surface 4 of said substrate 3 to form a drain contact. Said electrode may be, for example, gold-ammony deposited in a known manner.

As is clear from the foregoing, the method described above makes it possible to provide a particularly compact structure. In particular, a hollow gate structure can be obtained with a reduced gate drain capacitance in a manner that allows the source and drain regions to self-align to the hollow gate structure. Since the hollow gate structure is provided before, rather than after, the introduction of impurities to form the semiconductor and source regions, the possibility of misalignment of the central hole of the gate finger with respect to the semiconductor region is eliminated or At the very least, alignment tolerances can be minimized.

Furthermore, by using anisotropic etching to form windows for introducing impurities to form the source and semiconductor regions, the source and semiconductor regions can be self-aligned to the gate structure. Furthermore,
Alignment tolerances can be further minimized because the same window can be used for all silicidation steps and the contact window for source metallization.

It will be appreciated, of course, that the method described above is also suitable for manufacturing semiconductor devices other than vertical IGFETs. In particular, the method in which an insulating material is grown and then anisotropically etched to leave an insulating material filling the gap between the conductive gate finger strips Ba of the gate fingers is suitable for semiconductors or other conductive layers provided on the substrate, such as charge coupled devices. It can be applied to the following electrodes.

The present invention is of course applicable to semiconductor devices made of materials other than silicon. Although the present invention finds particular application with respect to IGFETs having a comb structure,
It can also be applied to other cellular structures.

Other variations will be apparent to those skilled in the semiconductor art, such as those who design, manufacture and/or use semiconductor devices, after reading the description of the invention.

Although this application has been claimed with particular combinations of features, the claimed invention resides in every novel feature or combination thereof, expressly described or suggested, or obvious to one skilled in the art. It also includes all combinations or variations of a feature or one or more of the features. Applicant hereby discloses that new claims of such features and/or combinations of such features may be filed during the pendency of this application or any other application derived from this application. I'll keep it.

[Brief explanation of the drawing]

Figures 1a to 1e are partial cross-sectional views showing states at each step of the method of the present invention for manufacturing an IGFBT, and Figure 2 is an IGF produced by the method of the present invention! FIG. 3 is a cross-sectional view taken along It-II in FIG. 3 showing a part of the ET, and FIG. 3 is a plan view of a part of the IGFIET shown in FIG. 1... Semiconductor 2... Source region 2a,
7.10... Opening 3... Drain area 4.
5... Main surface 6, 61... Gate layer 8.
...Gate finger 8a...Gate finger strip 3'a...Outer edge 8゛ha of gate finger...
・Inner edge of gate finger 9... Bus bar 9
a... Edge of bus bar 11... Super heat-resistant metal silicide 12... P-type semiconductor region 12a... Edge of p-type semiconductor region 13... Channel portion 14... Single crystal silicon substrate 15... ...High resistance n-type single crystal silicon 16...Oxide layer 16', 19...
Insulating material 17... Fillet 20... Resist layer 20a... Masking area 21... Hole 21
a...Edge of hole 23...Source metallized portion 2
4...Gate metallized portion 61'...Gate layer surface 62...Insulating layer 63...Etching resistant layer Patent applicant: NV Philips Fluylan Pen Fabricken

Claims (1)

[Claims] 1. A conductive layer is provided on the surface of the semiconductor, in which case the conductive layer is formed with at least one opening, and an insulating material is grown on the surface to cover said conductive layer. In the method of manufacturing a semiconductor device as described above, the opening is made small enough so that the insulating material grown on the edge of the conductive layer bounding the opening meets and closes said opening; Continue the growth for a sufficiently long period of time to anisotropically etch this insulating material towards said surface to expose the conductive layer and/or to form a semiconductor surface larger than the opening and not covered by the conductive layer. A method for manufacturing a semiconductor device, characterized in that a window is formed in an insulating material covering a portion of the conductive layer, and an anisotropic etching leaves the insulating material at the edges of the conductive layer so that the opening remains closed. 2. The method according to claim 1, wherein an insulating layer is provided between the surface and the conductive layer. 3. at least one opening is formed within an area of the conductive layer that is larger than the opening and bounded by one or more areas of the semiconductor surface not covered by the conductive layer; anisotropic etching; 3. A method as claimed in claim 1 or claim 2, in which the window or windows are formed in the insulating material covering the or each area. 4. The conductive layer is formed with a plurality of said openings and is divided into a plurality of regions by a portion of the semiconductor surface larger than the openings, each region having at least one of the openings. Method described. 5. A method as claimed in claim 3 or 4, in which one or each region has more than one of said openings. 6. The method according to any one of claims 3 to 5, wherein impurities are introduced into the semiconductor through a window. 7. The electrically conductive region is elongated and the opening extends along the length of the electrically conductive layer to form two electrically conductive region strips. the method of. 8. A method according to any one of claims 1 to 6, in which metal is deposited on the surface exposed by the anisotropic etching to reduce its resistivity. 9. Claim 1, wherein at least the surface of the semiconductor and/or the surface of the conductive layer is made of silicon oxide, and furthermore, a super heat-resistant metal silicide is formed on the exposed surface by anisotropic etching. The method according to any one of items 6 to 6. 10. Providing a conductive gate layer on the surface of the semiconductor to form an insulated gate structure having an opening therein and a conductive gate region, and introducing impurities into the semiconductor to align with the insulated gate structure. A method for manufacturing an insulated gate field effect transistor, comprising forming a channel region of the opposite conductivity type beneath a source region and a gate region of one conductivity type, and growing an insulating material on said surface to cover the insulated gate structure. The opening in the gate region is made small enough and the growth of insulating material is made sufficiently large that the insulating material grown on the edge of the conductive gate layer bounding the opening meets and closes said opening. the insulating material remains at the edges of the insulated gate structure to bound at least a portion of the window formed in the insulating material by the anisotropic etch and close the opening in the gate region. A method for manufacturing an insulated gate field effect transistor, characterized by etching anisotropically toward the surface of a semiconductor, introducing impurities, and forming a source region and a channel region through a window. 11. The source region is formed in a semiconductor region of opposite conductivity type, such that a portion of this semiconductor region provides a channel region, and a masking region and a window are provided between the masking region or the source not covered with insulating material. The semiconductor region is shorted to the source region by one or more masking regions extending across the window formed by the anisotropic etch to form one or more exposed portions of the region. etching away the exposed portion of the region to expose the underlying portion or portion of the semiconductor region; removing the masking region; and providing metallization within the window to short the exposed portion of the semiconductor region to the source region. The method according to claim 10. 12. The window is elongated and provided in such a way that one or each masking area extends completely across the width of the window or only partially across the length of the window. the method of. 13. The electrically conductive region is elongated and the opening extends along the length of the electrically conductive layer to form two electrically conductive region strips. the method of. 14. The conductive layer is provided such that the conductive region is elongated and the opening extends along the length of the conductive region to form two conductive region strips, and the anisotropic etching of the insulating material is performed. forming respective windows on respective long sides of the gate region, and impurities introduced into the semiconductor to form respective source regions aligned with each long edge of the gate region and respective channel regions underlying each gate region strip; A method according to any one of claims 10 to 12. 15. The method according to any one of claims 10 to 14, wherein the anisotropic etching exposes the surface of the gate layer. 16. A method as claimed in any one of claims 10 to 14, in which metal is deposited on the surface exposed by the anisotropic etching to reduce its resistivity. 17. Claim 10, wherein at least the surface of the semiconductor and/or the surface of the conductive layer is made of silicon oxide, and furthermore, a super heat-resistant metal silicide is formed on the exposed surface by anisotropic etching. Any one of items 1 to 16
The method described in section.