JPS63169066A - Thin film transistor element - Google Patents
Thin film transistor elementInfo
- Publication number
- JPS63169066A JPS63169066A JP41587A JP41587A JPS63169066A JP S63169066 A JPS63169066 A JP S63169066A JP 41587 A JP41587 A JP 41587A JP 41587 A JP41587 A JP 41587A JP S63169066 A JPS63169066 A JP S63169066A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- piled
- oxide film
- tpt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 6
- 239000002184 metal Substances 0.000 claims abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 150000002739 metals Chemical class 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 239000010408 film Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- LFVLUOAHQIVABZ-UHFFFAOYSA-N Iodofenphos Chemical compound COP(=S)(OC)OC1=CC(Cl)=C(I)C=C1Cl LFVLUOAHQIVABZ-UHFFFAOYSA-N 0.000 description 1
- 208000036366 Sensation of pressure Diseases 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- CUZMQPZYCDIHQL-VCTVXEGHSA-L calcium;(2s)-1-[(2s)-3-[(2r)-2-(cyclohexanecarbonylamino)propanoyl]sulfanyl-2-methylpropanoyl]pyrrolidine-2-carboxylate Chemical compound [Ca+2].N([C@H](C)C(=O)SC[C@@H](C)C(=O)N1[C@@H](CCC1)C([O-])=O)C(=O)C1CCCCC1.N([C@H](C)C(=O)SC[C@@H](C)C(=O)N1[C@@H](CCC1)C([O-])=O)C(=O)C1CCCCC1 CUZMQPZYCDIHQL-VCTVXEGHSA-L 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタに係り、特に薄膜トランジス
タの晶速動作に好適な薄膜トランジスタ素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor, and particularly to a thin film transistor element suitable for crystal fast operation of the thin film transistor.
最近、１９８６年（昭和６１年）春季、第３３回応用物
理学関係連合講演会予稿集３Ｐ−Ｅ−１２゜Ｐ、８３６
に記載のように周辺回路内蔵のアクティブトリクス液晶
ディスプレイの研究が盛んになってきた。アクティブマ
トリクス方式の周辺回路はＬにシフトレジスタとバツハ
ア回路で構成されるが、バッファ回路のトランジスタは
表示部内部の数百、数千個ものＴＰＴ’！ｉ−駆動させ
なければならないので、大電流駆動のトランジスタが要
求される。さて、上記のような性能をＴＰＴ （薄膜ト
ランジスタ）で実現しようとすると、現在のところ、多
結晶シリコンを用いたＭＯ８形ＴＰＴになると思われる
。これはａ）基板は安価なガラス基板を使うので６００
℃以下の低温プロセスでなければならない、ｂ）ａ−Ｓ
ｉ（アモルファスシリコン）ＴＰＴは移動度μｆｅが多
結晶シリコンのそれと比べて約２ケタ小さい、ｃ）Ｃｄ
Ｓｅは経時変化の問題がある。ｄ）バイポーラＴＰＴの
充分な特性は。Recently, Spring 1986 (Showa 61), 33rd Applied Physics Association Lecture Proceedings 3P-E-12゜P, 836
As described in , research into active trix liquid crystal displays with built-in peripheral circuits has become active. The peripheral circuit of the active matrix system consists of a shift register and a buffer circuit in L, but the transistors in the buffer circuit are hundreds or thousands of TPT'!'! Since it must be i-driven, a transistor capable of driving a large current is required. Now, if an attempt is made to achieve the above-mentioned performance with a TPT (thin film transistor), it is currently thought that an MO8 type TPT using polycrystalline silicon will be used. This is because a) an inexpensive glass substrate is used for the substrate, so it is 600 yen.
Must be a low temperature process below ℃, b) a-S
The mobility μfe of i (amorphous silicon) TPT is about two orders of magnitude smaller than that of polycrystalline silicon, c) Cd
Se has the problem of changing over time. d) What are the sufficient properties of bipolar TPT?
未だかつて出現していない等の理由によるものである。This is due to reasons such as it has never appeared before.
しかし、多結晶シリコンＴＰＴのμｆｅ（移動度）は単
結晶シリコンのそれと比べると約１ケタ小さいので、大
電流を得るためにはゲート幅Ｗを充分大きくしなければ
いけない（ここで、ゲート長りを短くするのは、ホトリ
ソプラノイの制約がある為、むやみに短くできない。）
結局。However, the μfe (mobility) of polycrystalline silicon TPT is about one order of magnitude smaller than that of single-crystal silicon, so the gate width W must be made sufficiently large to obtain a large current (here, the gate length must be cannot be shortened unnecessarily because of the photolithography restrictions.)
in the end.
表示部のＴＰＴと比較すると極めて大きなものになって
しまう。This is extremely large compared to the TPT of the display section.
多結晶シリコンＴＰＴのゲート電極は通常、単結晶ＮＭ
Ｏ５トランジスタと同じように製作する為。The gate electrode of polycrystalline silicon TPT is usually made of single crystal NM.
To manufacture it in the same way as an O5 transistor.
ゲート電極は多結晶シリコンが用いられる。単結晶シリ
コンのプロセスではゲート電極となる多結晶シリコンに
Ｐ（燐）をイオン打込みした後。Polycrystalline silicon is used for the gate electrode. In the single-crystal silicon process, P (phosphorus) ions are implanted into the polycrystalline silicon that will become the gate electrode.
９００℃〜１２００℃のＮｚ％’囲気中でアニールする
為、Ｐ（燐）が充分、活性化されてゲートｆｔ電極（多
結晶シリコン）のシート抵抗が充分低くなる。Since the annealing is performed in an Nz%' atmosphere at 900° C. to 1200° C., P (phosphorus) is sufficiently activated and the sheet resistance of the gate ft electrode (polycrystalline silicon) is sufficiently reduced.
りころが、アクティブマトリクス液晶ディスプレイ用に
製作される多結晶シリコンＴＰＴはガラス基板上に製作
するので、単結晶シリコンプロセスと同じような９００
℃〜１２００℃のアニールができない（ガラス基板が歪
むので）。その結果、 ＴＰＴのゲート電極（多結晶シ
リコン）のシート抵抗が単結晶のそれと比べると数ケタ
高くなる。このようなゲート電極を持つＴＰＴのゲート
部（第１図）にパルス電圧を加えた場合、涯抵抗の多結
晶シリコンゲートｆｆ１ＨとＴＰＴ自身の容量の為に、
ドレイン電流Ｉｂはゲート電極にパルス電圧を印加した
タイミングより充分遅れて変化する。これでは屯営な書
込み動作が行えない。The polycrystalline silicon TPT manufactured for active matrix liquid crystal displays is manufactured on a glass substrate, so the process is similar to the single crystal silicon process.
Annealing at temperatures between 1200°C and 1200°C is not possible (because the glass substrate will be distorted). As a result, the sheet resistance of the TPT gate electrode (polycrystalline silicon) is several orders of magnitude higher than that of a single crystal. When a pulse voltage is applied to the gate part (Fig. 1) of a TPT having such a gate electrode, due to the capacitance of the polycrystalline silicon gate ff1H and the TPT itself,
The drain current Ib changes with a sufficient delay from the timing at which the pulse voltage is applied to the gate electrode. This makes it impossible to perform regular write operations.
そこで、上記問題点を解決する為、バッファ回路のＴＦ
Ｔを第１図の構成にした。即ち、ゲート電極である多結
晶シリコン上に数カ所、ゲート部ｍ ｆｔ極を接触さす
事により解決される。Therefore, in order to solve the above problem, the TF of the buffer circuit
T has the configuration shown in Figure 1. That is, this problem can be solved by bringing the gate m ft pole into contact with the polycrystalline silicon serving as the gate electrode at several locations.
即ち、第１図のゲート電極は電気的に見た場合、本来の
ゲート幅Ｗにより、かなり、ゲート幅Ｗが短く見える。That is, when the gate electrode in FIG. 1 is electrically viewed, the gate width W appears to be considerably short due to the original gate width W.
その結果、ゲート電極の抵抗が小さくなり高速動作が可
能になる。As a result, the resistance of the gate electrode is reduced and high-speed operation is possible.
以下、本発明の一実施例を第３図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
ａ）ガラス基板上にＬＰＣＶＤ （Ｌｏｗ Ｐｒｅｓｓ
ｕｒｅＣｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｆ
ｉｏｎ）、プラズマＣＶＤ等の公知の技術により、多結
晶シリコン１を堆積し、島状にカットする。次にＬＰＧ
ＶＤ、 ＡＰＣＶＤ（Ａｔｍｏｓｐｈｅｒｉｃ Ｐｒｅ
ｓｓｕｒｅ Ｃｈｅｍｉｃａｌ ＶａｐｏｒＤｅρｏｓ
ｉｆｉｏｎ）法などにより、ゲート絶縁膜となる酸化シ
リコン膜、ゲート電極となる多結晶シリコン膜２を順次
堆積し、ゲート部以外の多結晶シリコン膜２．酸化シリ
コン膜を除去する。a) LPCVD (Low Press
ureChemical Vapor Deposit
Polycrystalline silicon 1 is deposited by a known technique such as ion) or plasma CVD, and then cut into island shapes. Next, LPG
VD, APCVD (Atmosphere Pre
ssure Chemical VaporDeρos
A silicon oxide film, which will become a gate insulating film, and a polycrystalline silicon film 2, which will become a gate electrode, are sequentially deposited by a method such as ivion), and the polycrystalline silicon film 2. Remove the silicon oxide film.
ｂ） ｐ （燐）を全面にイオン打込みし、６０゜℃で
アニールする。その後、酸化シリコン膜を堆積し、その
後ゲート部のコンタクトホール４．及び、ソース、ドレ
イン部のコンタクトホール５を形成する。b) P (phosphorus) ions are implanted into the entire surface and annealed at 60°C. After that, a silicon oxide film is deposited, and then a contact hole 4 in the gate area is formed. Then, contact holes 5 for the source and drain portions are formed.
Ｃ）スパッタ法などによりＡＱを堆積し、その後ゲート
配線部３、ソース、ドレイン部６以外のＡＱを除去する
。C) Deposit AQ by sputtering or the like, and then remove AQ other than the gate wiring portion 3, source, and drain portions 6.
本発明によれば、ガラス基板上に製作された多結晶シリ
コンＴＰＴのゲートｆｆ電極の抵抗が見かけ上、小さく
見えるので、ＴＰＴの高速化の効果がある。According to the present invention, the resistance of the gate ff electrode of a polycrystalline silicon TPT fabricated on a glass substrate appears to be small, which has the effect of increasing the speed of the TPT.
第１図は本発明の一実施例のバッファ回路のＴＰＴの平
面図、第２図は従来のバッファ回路のＴＰＴの平面図、
第３図は本発明のＴＰＴの製造工程図である。FIG. 1 is a plan view of a TPT of a buffer circuit according to an embodiment of the present invention, FIG. 2 is a plan view of a TPT of a conventional buffer circuit,
FIG. 3 is a manufacturing process diagram of the TPT of the present invention.
Claims (1)
に対しゲート電極の少なくとも２ケ所以上の複数箇所に
コンタクト部を設け、配線金属を接触させる事を特徴と
する薄膜トランジスタ素子。1. A thin film transistor element, characterized in that contact portions are provided at at least two or more locations on the gate electrode to contact the first gate electrode with metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41587A JPS63169066A (en) | 1987-01-07 | 1987-01-07 | Thin film transistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41587A JPS63169066A (en) | 1987-01-07 | 1987-01-07 | Thin film transistor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63169066A true JPS63169066A (en) | 1988-07-13 |
Family
ID=11473166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41587A Pending JPS63169066A (en) | 1987-01-07 | 1987-01-07 | Thin film transistor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63169066A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0449123A2 (en) * | 1990-03-24 | 1991-10-02 | Sony Corporation | Liquid crystal display device |
-
1987
- 1987-01-07 JP JP41587A patent/JPS63169066A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0449123A2 (en) * | 1990-03-24 | 1991-10-02 | Sony Corporation | Liquid crystal display device |
| EP0723179A1 (en) * | 1990-03-24 | 1996-07-24 | Sony Corporation | Liquid crystal display device |
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