JPS6316897B2 - - Google Patents

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Publication number
JPS6316897B2
JPS6316897B2 JP9949981A JP9949981A JPS6316897B2 JP S6316897 B2 JPS6316897 B2 JP S6316897B2 JP 9949981 A JP9949981 A JP 9949981A JP 9949981 A JP9949981 A JP 9949981A JP S6316897 B2 JPS6316897 B2 JP S6316897B2
Authority
JP
Japan
Prior art keywords
plating
electrode
voltage
peripheral side
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9949981A
Other languages
Japanese (ja)
Other versions
JPS582017A (en
Inventor
Hiromitsu Tagi
Takeshi Nishio
Norya Sato
Kusuo Kukuhara
Shoji Kuroda
Masaaki Imada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9949981A priority Critical patent/JPS582017A/en
Publication of JPS582017A publication Critical patent/JPS582017A/en
Publication of JPS6316897B2 publication Critical patent/JPS6316897B2/ja
Granted legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は製造容易,安価にして、かつ諸特性の
安定した高電圧用セラミツクコンデンサの製造方
法に関するものである。 従来から誘電体,圧電体,半導体等の機能特性
を利用したセラミツク電子部品の電極材料として
は、磁器素体の表面にガラスフリツトが含まれて
いるAg,Ag−Pd,Ag−Pt,Ag−Ni等の貴金
属を主体とした焼付電極法が実用化されている。
しかし、近年の貴金属の高騰に伴ない、各メツキ
方法が開発されつつある。しかしながら、これら
の方法にも多くの欠点があり、例えば磁器素体面
に焼付銀電極を形成し、その後ニツケル電極,銅
電極を電極メツキ法により金属電極を設ける事も
可能であるが、この方法では焼付金属層表面が粗
面で多くの小孔が存在するため、メツキ処理にお
いてメツキ液がこの小孔内部に浸透し、焼付金属
層と磁器素体の接着強度を劣化させる欠点があつ
た。他の方法としては一般的に知られている無電
解メツキ法が用いられており、無電解ニツケルメ
ツキは最初に塩化スズと塩化パラジウムを化学的
反応により触媒活性化処理を施こす事が一般的で
あつた。 しかし、高電圧用セラミツクの電極として使用
する場合には多くの問題点がある。即ち、電極材
料及び関連材料の種類,取付方法によつて引張強
度(銀焼付電極に比べ1/2に低下)、さらには耐電
圧等の電気的特性(寿命テストによる特性劣化)
等が著しく劣化するものであつた。例えば磁器コ
ンデンサの電極を形成する場合、無電解ニツケル
メツキ方法はその工法性質上、基板全周表面上に
形成され易く、その場合は周側面の被膜を研削除
去して対向容量電極を形成するが、金属イオンが
粒子間あるいは周側面の粒界内部に浸透し、高電
圧を印加した場合に粒界に沿つて破壊が発生する
ものであつた。この場合、沿面耐電圧距離は基板
の厚みで決定し、電極周端部における電界の集中
によつて絶縁破壊が起り易く、基板の厚みを余り
薄くする事はできなく、さらに周側部も設計値よ
り深く研削する必要があつた。しかし、これらも
再現性が悪く、数多くの問題点を持つていた。 また、これらの方法に対し部分メツキ方法とし
ては、磁器表面に所要パターンの金属層を形成す
るに際し、あらかじめ磁器表面の所要部に樹脂の
メツキレジストを付与し、次いで磁器表面を活性
化した後メツキレジストを除去し、その後無電解
メツキを施こして磁器表面に金属層を形成する方
法、また真空蒸着法、フオトエツチング法等、
種々の方法がある。しかし、いずれも高電圧用セ
ラミツクコンデンサの電極としては満足する結果
が得られない。即ち、従来から知られているメツ
キ付与方法ではメツキの密着性が悪く、特に高電
圧を目的としたコンデンサ製品の素体厚みは0.8
〜10m/mと厚く、形状は4.5〜16φm/mと種々
あり、量産性を考慮した場合困難なものであつ
た。さらに、破壊電圧を少しでも高めるため、磁
器表面の電極部に何m/mかの縁を設ける方法、
周側部にガラスを塗布する方法等、数多くの方法
が用いられているが、決定的な方法はないもので
あつた。これは誘電体材料自体さらには電極材
料、形成方法等と密接な関係にある事が本発明者
らの実験によつて明確になつた。 本発明は上記のような数多くの欠点を除去し、
寿命特性において著しく安定した特性を有する高
電圧用セラミツクコンデンサの製造方法を提案す
るものである。 即ち、本発明はAg成分99.5〜0.5wt%、Ni成分
0.5〜99.5wt%の比率範囲内の混合粉または合金
粉よりなる下地活性電極材料と有機質ワニスから
なるペーストを、表面粒度3〜7μmの範囲内に研
磨された誘電体セラミツク基板にその周側部が残
るように塗布し、その後300〜800℃の温度範囲で
熱処理を施こし上記基板上に1.5μm以下の金属粒
子層を形成し、その後Pd,Ptイオンの1種また
は2種が含まれている溶液中で前記AgおよびNi
を前記PdあるいはPtで置換処理し、その後無電
解メツキ液によりニツケル,銅等の金属導電被膜
を形成し、その後基板の周側面を5μm以下の表面
粗度に研磨した事を特徴とする高電圧用セラミツ
クコンデンサの製造方法であり、本発明の方法に
よつて得られた高電圧用セラミツクコンデンサは
従来迄の焼付銀電極法によつて得られた物に対
し、高温高湿度中におけるAgイオンマイグレー
シヨンによる特性劣化が著しく少なく、さらに高
電圧に対しても安定なもので、これらは本発明の
電極材料及び工法さらには設計等の組み合せによ
つてはじめて効果が生ずるものである。 以下、本発明を実施例を挙げ説明する。 まず、誘電体セラミツク基板としては、
SrTiO3−CaTiO3−Bi2O3系の基板を用い、厚み
4.0m/m、形状15φm/mのものを表面研磨によ
り表面粗度3〜7μmに研磨した。 その後、周側部が残るようなマスクを用い、本
発明の下地活性電極材料を印刷塗布し、焼付処理
を行つた。 なお、Ag−Ni成分の下地活性用電極ペースト
作成方法としては、粒径0.2μmのAg粉末、粒径
0.5μmのNi粉末を用い電極金属成分とし、この金
属成分としては約3〜30wt%、セルローズ系、
アクリル系等の有機バインダ約3〜15wt%、テ
レピン油、ブチルカルビートルアセテート等の溶
剤成分約55〜82wt%とし、このペーストを印刷
用としては約30000〜60000cps、吹付用としては
約100〜400cpsの粘度に調整し、セラミツク基板
の表裏に付与した。その後、80〜100℃の温度で
乾燥し溶剤を蒸発させた後、電気炉を用いて300
〜800℃の温度範囲で焼付を行い1.5μm以下の金
属微粒子層を形成した。ここで、300〜800℃の間
で焼付を行う事の必要性はセラミツク基板面に強
固な下地金属粒子層を形成するためであり、熱処
理温度が300℃未満では有機物質が完全に飛散せ
ず、ニツケルまたは銅の無電解メツキが不完全と
なり、素体と電極との接着強度が低下し、また電
気特性においては破壊電圧の低下を招き、さらに
は損失角が悪化するため好ましくない、また、
800℃を越える処理温度では金属粒子層が一部酸
化され、メツキが困難になる。かつ電気特性も劣
化するため好ましくない。 上記範囲内の温度で熱処理を行い1.5μm以下
(0は含まず)の金属粒子層を形成後、Pd,Ptイ
オンの1種または2種が0.05wt%含まれている溶
液中で1分間置換処理を施こす。なお、この置換
処理は以下のように行われる。 2Ag+Pd++→Pd+2Ag+ Ni+Pd++→Pd+Ni++ 2Ag+Pt++→Pt+2Ag+ Ni+Pt++→Pt+Ni++ そして、その後ニツケル無電解メツキとして
は、硫酸ニツケルに次亜燐酸ナトリウム(または
ヒドラジン、水素化ホウ素化合物等)を含むメツ
キ液に浸漬してニツケル金属膜を形成した。ま
た、銅メツキとしては硫酸銅、還元剤としてはホ
ルマリン、錯化剤としてはロツシエル塩、アルカ
リ剤としては水酸化ナトリウムを用い、銅の無電
解メツキを行つた。 ここで、本発明においてペースト焼付後の厚さ
が1.5μm以下(0は含まず)の金属粒子層の上に
Pd,Pt等の金属イオンを析出させ、さらにNiま
たはCuの無電解メツキを行う事によつて電極と
しての機能が初めて生ずるものである。なお、従
来からコンデンサ等の電極材料として用いられて
いる焼付銀は焼付後の膜厚が3〜20μmと厚く形
成する必要があり、その膜自体が電極層として利
用できるものであるが、本発明の焼付後の金属粒
子層は1.5μm以下と著しく薄く、それ自体では電
極機能としての働きはなく、また半田付もできな
いもので、その後のPd,Pt等のイオン析出後、
無電解ニツケルまたは銅メツキによつて初めて電
極機能として利用でき、半田付も可能になるもの
である。なお、本発明は焼付後の金属粒子層とし
て平均1.5μm以下の厚みで存在しておれば充分に
その機能を発揮する事ができるもので、高電圧用
セラミツクコンデンサの電極として利用した場
合、1.5μmを越える厚みではメツキ後の基板との
接着強度が著しく低下し、また無電解メツキを施
こす場合に所定以外の部分にメツキが付着して耐
電圧が低下し、特に湿中負荷寿命特性において電
気特性が劣化する。 そして、本発明の誘電体セラミツク基板表裏面
を粗度3〜7μmの範囲内に研磨するのは、電極と
の接着性を強固にし、耐電圧のバラツキをなく
し、コロナ電圧の向上と共に安定した特性値を得
るためで、3μm未満では接着性が低下し、耐電圧
も劣化する。一方、7μmを越える粗度では誘電正
接が悪化し、湿度特性において電気特性の劣化が
著しい。また、金属導電膜を形成後、素体の周側
面を5μm以下に研磨することの必要性は、コロナ
電圧の向上と共に下地活性金属であるAg−Ni成
分の湿中におけるセラミツク粒界へのマイグレー
シヨンの現象を防止し、さらにはAg−Ni粒子の
ウイスカ生成現象を防止して安定した特性を得る
ためであり、5μmを越える表面粗さでは特性のバ
ラツキがあり、湿度寿命において著しく低下する
ため好ましくない。 なお、従来から知られている一般的な無電解メ
ツキ法、即ち最初に塩化スズと塩化パラジウムを
化学的反応により触媒活性化処理を施こし、その
後無電解メツキを行う方式では、素体の全面に付
着し、さらにはSnイオンの働きによつて高電圧
用の電極として利用した場合、湿中寿命において
著しく低下するものであつた。ここで、一般的な
考え方としては全面メツキ後、周側部を研磨する
方法も考えられるが、これも粒界への拡散現象が
起き電気特性が悪く、高電圧用コンデンサへの応
用には不向きであつた。また、従来から知られて
いる焼付銀電極では湿中寿命においてAgイオン
マイグレーシヨンが著しく、これらの防止のため
にガラス等を周側部に塗布する方法が行われてい
たが、完全ではなく、本発明の方法によつて初め
て完全な高電圧用セラミツクコンデンサを得る事
が可能になつた。 次に、本発明方法により得られた高電圧用セラ
ミツクコンデンサの特性値を各条件と共に下記の
表に示す。ここで、高電圧用セラミツクコンデン
サの作製としては上記に明記した方法で作製し、
それにリード線をPb−Sn系の半田を用いて取付
け、被覆樹脂としてはフエノール系を用い高電圧
用セラミツクコンデンサとした。そして、表中の
各値は10ケの平均値であり、85℃・85%RHの湿
度負荷寿命は最初の1ケが絶縁破壊(以下パンク
と略す)した時間の値である。
The present invention relates to a method for manufacturing a high-voltage ceramic capacitor that is easy to manufacture, inexpensive, and has stable characteristics. Conventionally, electrode materials for ceramic electronic components that utilize the functional properties of dielectrics, piezoelectrics, semiconductors, etc., include Ag, Ag-Pd, Ag-Pt, and Ag-Ni, which contain glass frit on the surface of the ceramic body. The baked electrode method, which uses precious metals such as, has been put into practical use.
However, with the recent rise in the price of precious metals, various plating methods are being developed. However, these methods also have many drawbacks; for example, it is possible to form baked silver electrodes on the surface of the porcelain body and then provide metal electrodes with nickel electrodes and copper electrodes by electrode plating, but this method Since the surface of the baked metal layer is rough and has many small pores, the plating solution penetrates into the small holes during the plating process, resulting in a disadvantage that the adhesive strength between the baked metal layer and the porcelain body deteriorates. Another method is the commonly known electroless plating method, which typically first undergoes a catalytic activation treatment through a chemical reaction between tin chloride and palladium chloride. It was hot. However, there are many problems when using it as a high voltage ceramic electrode. In other words, depending on the type of electrode material and related materials and the mounting method, tensile strength (reduced to 1/2 compared to silver baked electrodes) and electrical properties such as withstand voltage (characteristics deteriorate due to life test)
etc. were significantly deteriorated. For example, when forming the electrodes of a ceramic capacitor, the electroless nickel plating method tends to form them on the entire circumferential surface of the substrate due to the nature of the method. Metal ions penetrated between grains or inside the grain boundaries on the peripheral side, and when a high voltage was applied, destruction occurred along the grain boundaries. In this case, the creepage withstand voltage distance is determined by the thickness of the board, and dielectric breakdown is likely to occur due to concentration of electric field at the electrode peripheral edge, so the board thickness cannot be made too thin, and the peripheral side part is also designed It was necessary to grind deeper than the specified value. However, these methods also had poor reproducibility and many problems. In contrast to these methods, a partial plating method involves applying a resin plating resist to the required portions of the porcelain surface in advance, and then activating the porcelain surface before plating to form a metal layer with a desired pattern on the porcelain surface. Methods such as removing the resist and then applying electroless plating to form a metal layer on the porcelain surface, vacuum evaporation method, photo etching method, etc.
There are various methods. However, none of these methods yields satisfactory results as electrodes for high-voltage ceramic capacitors. In other words, the adhesion of plating is poor with conventional plating methods, and the thickness of capacitor products intended for high voltage applications is 0.8 mm.
It is as thick as ~10m/m, and has various shapes ranging from 4.5 to 16φm/m, making it difficult to mass-produce it. Furthermore, in order to increase the breakdown voltage as much as possible, there is a method of providing an edge of several m/m on the electrode part of the porcelain surface,
Many methods have been used, such as applying glass to the peripheral side, but there is no definitive method. The inventors' experiments have revealed that this is closely related to the dielectric material itself, as well as the electrode material, formation method, etc. The present invention eliminates many of the drawbacks mentioned above and
This paper proposes a method for manufacturing high voltage ceramic capacitors that have extremely stable lifetime characteristics. That is, in the present invention, the Ag component is 99.5 to 0.5 wt%, the Ni component is
A paste consisting of a base active electrode material consisting of a mixed powder or alloy powder in a ratio range of 0.5 to 99.5 wt% and an organic varnish is applied to a dielectric ceramic substrate polished to a surface grain size of 3 to 7 μm on its peripheral side. After that, heat treatment is performed at a temperature range of 300 to 800℃ to form a metal particle layer of 1.5 μm or less on the substrate, and then a layer of metal particles containing one or two of Pd and Pt ions is applied. The Ag and Ni in solution
is replaced with Pd or Pt, and then a metal conductive film of nickel, copper, etc. is formed using an electroless plating solution, and then the peripheral side of the substrate is polished to a surface roughness of 5 μm or less. The high-voltage ceramic capacitor obtained by the method of the present invention exhibits less Ag ion migration in high temperature and high humidity than those obtained by the conventional baked silver electrode method. The deterioration of characteristics due to heat is extremely small, and it is also stable against high voltages, and these effects can only be achieved by combining the electrode materials and construction methods of the present invention, as well as the design. Hereinafter, the present invention will be explained with reference to Examples. First, as a dielectric ceramic substrate,
Using SrTiO 3 −CaTiO 3 −Bi 2 O 3 based substrate, the thickness
4.0 m/m and a shape of 15 φm/m was surface polished to a surface roughness of 3 to 7 μm. Thereafter, the base active electrode material of the present invention was applied by printing using a mask that left the peripheral side portion, and a baking process was performed. In addition, the method for preparing the electrode paste for base activation of the Ag-Ni component is to use Ag powder with a particle size of 0.2 μm,
0.5 μm Ni powder is used as the electrode metal component, and the metal component is about 3 to 30 wt%, cellulose type,
The organic binder such as acrylic is approximately 3 to 15 wt%, and the solvent component is approximately 55 to 82 wt% such as turpentine oil or butylcarbyl acetate.This paste is approximately 30,000 to 60,000 cps for printing, and approximately 100 to 400 cps for spraying. The viscosity was adjusted to , and applied to the front and back of a ceramic substrate. Then, after drying at a temperature of 80 to 100℃ to evaporate the solvent,
Baking was performed at a temperature range of ~800°C to form a layer of metal fine particles of 1.5 μm or less. Here, it is necessary to perform baking between 300 and 800℃ in order to form a strong base metal particle layer on the ceramic substrate surface, and if the heat treatment temperature is lower than 300℃, organic substances will not be completely scattered. , the electroless plating of nickel or copper becomes incomplete, the adhesion strength between the element body and the electrode decreases, and in terms of electrical properties, it causes a decrease in breakdown voltage, and furthermore, the loss angle worsens, which is undesirable.
At processing temperatures exceeding 800°C, the metal particle layer is partially oxidized, making plating difficult. Moreover, the electrical characteristics are also deteriorated, which is not preferable. After heat treatment at a temperature within the above range to form a metal particle layer of 1.5 μm or less (not including 0), replace for 1 minute in a solution containing 0.05 wt% of one or both of Pd and Pt ions. Apply processing. Note that this replacement process is performed as follows. 2Ag+Pd ++ →Pd+2Ag + Ni+Pd ++ →Pd+Ni ++ 2Ag+Pt ++ →Pt+2Ag + Ni+Pt ++ →Pt+Ni ++ Then, for nickel electroless plating, nickel sulfate is mixed with sodium hypophosphite (or hydrazine, boron hydride). A nickel metal film was formed by immersing it in a plating solution containing a chemical compound, etc.). Further, electroless plating of copper was performed using copper sulfate as the copper plating, formalin as the reducing agent, Rothsiel's salt as the complexing agent, and sodium hydroxide as the alkaline agent. Here, in the present invention, on the metal particle layer with a thickness of 1.5 μm or less (not including 0) after baking the paste,
The function as an electrode is created for the first time by depositing metal ions such as Pd and Pt, and then electroless plating with Ni or Cu. Incidentally, baked silver, which has conventionally been used as an electrode material for capacitors, etc., needs to be formed with a thick film thickness of 3 to 20 μm after baking, and the film itself can be used as an electrode layer. The metal particle layer after baking is extremely thin, less than 1.5μm, and does not function as an electrode by itself, nor can it be soldered.After the subsequent ion precipitation of Pd, Pt, etc.,
Electroless nickel or copper plating can be used for the first time as an electrode function, and soldering is also possible. The present invention can fully exhibit its function as long as the metal particle layer after baking has an average thickness of 1.5 μm or less, and when used as an electrode for a high-voltage ceramic capacitor, If the thickness exceeds μm, the adhesive strength with the board after plating will drop significantly, and when electroless plating is applied, the plating will adhere to areas other than the designated areas, reducing the withstand voltage, especially in terms of humidity load life characteristics. Electrical characteristics deteriorate. Polishing the front and back surfaces of the dielectric ceramic substrate of the present invention to a roughness of 3 to 7 μm strengthens the adhesion with the electrodes, eliminates variations in withstand voltage, and improves corona voltage and stable characteristics. This is to obtain a value, and if it is less than 3 μm, the adhesiveness will decrease and the withstand voltage will also deteriorate. On the other hand, if the roughness exceeds 7 μm, the dielectric loss tangent deteriorates, and the electrical characteristics deteriorate significantly in terms of humidity characteristics. Furthermore, after forming the metal conductive film, it is necessary to polish the peripheral surface of the element body to a thickness of 5 μm or less to improve the corona voltage and to prevent the migration of the Ag-Ni component, which is the underlying active metal, to the ceramic grain boundaries in humidity. This is to prevent the phenomenon of yellowing and whisker generation of Ag-Ni particles to obtain stable characteristics.If the surface roughness exceeds 5μm, the characteristics will vary and deteriorate significantly over the humidity life. Undesirable. In addition, in the conventionally known general electroless plating method, in which tin chloride and palladium chloride are first subjected to a catalytic activation treatment through a chemical reaction, and then electroless plating is performed, the entire surface of the element body is Furthermore, when used as a high-voltage electrode due to the action of Sn ions, its life in humidity was significantly reduced. Here, a general idea is to polish the peripheral side after plating the entire surface, but this also causes a diffusion phenomenon to the grain boundaries, resulting in poor electrical properties and is not suitable for application to high-voltage capacitors. It was hot. In addition, conventionally known baked silver electrodes suffer from significant Ag ion migration during their lifetime in humidity, and in order to prevent this, methods have been used to coat the peripheral sides with glass, etc., but this is not perfect. By the method of the present invention, it has become possible to obtain a complete high voltage ceramic capacitor for the first time. Next, the characteristic values of the high voltage ceramic capacitor obtained by the method of the present invention are shown in the table below along with various conditions. Here, the high voltage ceramic capacitor is manufactured using the method specified above.
Lead wires were attached to it using Pb-Sn solder, and a phenol-based coating resin was used to create a high-voltage ceramic capacitor. Each value in the table is the average value of 10 pieces, and the humidity load life at 85°C and 85% RH is the value of the time at which the first piece breaks down (hereinafter abbreviated as puncture).

【表】【table】

【表】 (注) * 本発明請求範囲外
上記表より明らかなように、本発明の電極材料
及び取付方法、加工方法によつて作られた高電圧
用セラミツクコンデンサの諸特性において、No.
1,10,11,16,22,23,28,32は本発明請求範
囲外の比較例である。そしてNo.1〜10迄はAg−
Ni成分の比率を変化させたもので、ペーストの
熱処理温度は400℃一定、熱処理後のAg−Ni金
属粒子層の平均厚みを0.5μm一定、セラミツク素
子表面及び周側部の表面粗さを平均5μm,2μmと
した場合の試料であり、No.1のAg成分のみでは
破壊電圧、寿命耐湿負荷特性において著しく悪い
ものであつた。また、No.10のようにNi成分のみ
ではNiメツキの付着性が悪く、諸特性も低いも
のであつた。一方、No.2〜9は著しく良好な特性
を示しており、特にNo.6,7は破壊電圧、コロナ
電圧も高く優秀なものである。次いで、No.11〜16
はペーストの熱処理温度を変化させた例であり、
表からも解るように最適温度は400〜550℃前後で
あり、No.11の低い温度及びNo.16の高い温度の場合
はいずれも諸特性が悪いものであつた。さらに、
No.17〜22迄は熱処理後のAg−Ni成分の金属粒子
層の厚みを変化させたもので、最適厚みは0.3〜
0.8μm前後であり、No.22のように厚くなると特性
が劣化し好ましくない。なお、表には示していな
いがNo.22のように1.5μmを越える厚みになると無
電解メツキ後の接着強度が著しく低下する。ま
た、上記表の実施例においてNo.1〜32迄は無電解
メツキとしてニツケルメツキを施こしたものであ
り、これらはニツケルメツキ厚として約1.5μm付
着している。ここで、一般的な考え方ではニツケ
ルメツキ厚みと接着強度との関係があるように思
われるが、本発明の電極形成方法ではほとんど差
が認められず、メツキ厚みとしては1〜3μm前後
で充分であつた。 また、No.23〜28は誘電体セラミツク素体表面を
研磨した例であり、本発明の範囲内のNo.24〜27は
特性が良好で、特に4〜6μmの表面粗度の場合が
破壊電圧が著しく向上する事が認められた。な
お、本実施例には示していないが、0.1〜0.5μm程
度迄研磨した場合は破壊電圧が10kV/mm以下に
劣下し、他の特性も低いものであつた。No.29〜32
は電極形成後、素子の周側面を研磨した場合の例
で、この場合は粗度が小さければ小さい程良好
で、0.5μmのNo.29は優秀なものであつた。No.32は
6μmと粗く、電気特性は劣化の傾向にあつた。さ
らに、No.33〜35はCuメツキを施こした例であり、
Niメツキに比べて少し特性は低下しているが、
実用的には全く問題がなく、優秀なものであつ
た。 以上のように本発明の方法によつて作製した高
電圧用セラミツクコンデンサは、特性的に著しく
安定しており、工業的量産化に適した産業的価値
の大なる製造方法である。
[Table] (Note) * Outside the scope of the claims of the present invention As is clear from the table above, the high voltage ceramic capacitor made using the electrode material, mounting method, and processing method of the present invention ranks No. 1 in terms of various characteristics.
1, 10, 11, 16, 22, 23, 28, and 32 are comparative examples outside the scope of the claims of the present invention. And No. 1 to 10 are Ag−
The ratio of Ni components is changed, the heat treatment temperature of the paste is constant at 400℃, the average thickness of the Ag-Ni metal particle layer after heat treatment is constant at 0.5 μm, and the surface roughness of the ceramic element surface and peripheral side is average. These are samples with a thickness of 5 μm and 2 μm, and with only the No. 1 Ag component, the breakdown voltage and lifetime moisture load resistance characteristics were extremely poor. Further, as in No. 10, when using only the Ni component, the adhesion of Ni plating was poor and the various properties were also poor. On the other hand, Nos. 2 to 9 exhibited extremely good characteristics, and Nos. 6 and 7 in particular were excellent in terms of breakdown voltage and high corona voltage. Next, No.11-16
is an example of changing the heat treatment temperature of the paste,
As can be seen from the table, the optimum temperature is around 400 to 550°C, and both the low temperature of No. 11 and the high temperature of No. 16 had poor characteristics. moreover,
Nos. 17 to 22 have different thicknesses of the Ag-Ni component metal particle layer after heat treatment, and the optimal thickness is 0.3 to 22.
It is around 0.8 μm, and if it is thick like No. 22, the characteristics will deteriorate and it is not preferable. Although not shown in the table, when the thickness exceeds 1.5 μm like No. 22, the adhesive strength after electroless plating decreases significantly. Further, in the examples shown in the above table, Nos. 1 to 32 were nickel plated as electroless plating, and the nickel plating thickness of these was about 1.5 μm. Generally speaking, there seems to be a relationship between the thickness of the nickel plating and the adhesive strength, but with the electrode forming method of the present invention, almost no difference is observed, and a thickness of the plating of around 1 to 3 μm is sufficient. Ta. In addition, Nos. 23 to 28 are examples of polished surfaces of dielectric ceramic bodies, and Nos. 24 to 27 within the scope of the present invention have good characteristics, especially when the surface roughness is 4 to 6 μm. It was observed that the voltage was significantly improved. Although not shown in this example, when polished to about 0.1 to 0.5 μm, the breakdown voltage decreased to 10 kV/mm or less, and other properties were also poor. No.29~32
is an example in which the peripheral side of the element was polished after electrode formation; in this case, the smaller the roughness, the better, and No. 29 with a roughness of 0.5 μm was excellent. No.32 is
It was as rough as 6 μm, and its electrical properties tended to deteriorate. Furthermore, Nos. 33 to 35 are examples of Cu plating,
Although the characteristics are slightly lower than Ni-metsuki,
There were no practical problems at all, and it was excellent. As described above, the high voltage ceramic capacitor produced by the method of the present invention has extremely stable characteristics and is a manufacturing method of great industrial value suitable for industrial mass production.

Claims (1)

【特許請求の範囲】[Claims] 1 Ag成分99.5〜0.5wt%,Ni成分0.5〜99.5wt
%の比率範囲内の混合粉または合金粉よりなる下
地活性電極材料と有機質ワニスからなるペースト
を、表面粗度3〜7μmの範囲内に研摩された誘電
体セラミツク基板にその周側部が残るように塗布
し、その後300〜800℃の温度範囲で熱処理を施こ
し上記基板上に1.5μm以下の金属粒子層を形成
し、その後Pd,Ptイオンの1種または2種が含
まれている溶液中で前記AgおよびNiを前記Pdあ
るいはPtで置換処理し、その後無電解メツキ液
によりニツケルあるいは銅の金属導電被膜を形成
し、その後上記基板の周側面を5μm以下の表面粗
度に研摩した事を特徴とする高電圧用セラミツク
コンデンサの製造方法。
1 Ag component 99.5-0.5wt%, Ni component 0.5-99.5wt
A paste consisting of a base active electrode material consisting of a mixed powder or alloy powder within a ratio of 1.5% and an organic varnish is applied to a dielectric ceramic substrate polished to a surface roughness of 3 to 7 μm so that its peripheral side remains. After that, heat treatment is performed at a temperature range of 300 to 800℃ to form a metal particle layer of 1.5 μm or less on the substrate, and then coated in a solution containing one or both of Pd and Pt ions. Then, the Ag and Ni were replaced with the Pd or Pt, and then a nickel or copper metal conductive film was formed using an electroless plating solution, and then the peripheral side of the substrate was polished to a surface roughness of 5 μm or less. A manufacturing method for high-voltage ceramic capacitors.
JP9949981A 1981-06-25 1981-06-25 Method of producing high voltage ceramic condenser Granted JPS582017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9949981A JPS582017A (en) 1981-06-25 1981-06-25 Method of producing high voltage ceramic condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9949981A JPS582017A (en) 1981-06-25 1981-06-25 Method of producing high voltage ceramic condenser

Publications (2)

Publication Number Publication Date
JPS582017A JPS582017A (en) 1983-01-07
JPS6316897B2 true JPS6316897B2 (en) 1988-04-11

Family

ID=14248971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9949981A Granted JPS582017A (en) 1981-06-25 1981-06-25 Method of producing high voltage ceramic condenser

Country Status (1)

Country Link
JP (1) JPS582017A (en)

Also Published As

Publication number Publication date
JPS582017A (en) 1983-01-07

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