JPS63168754A - Memory error check system - Google Patents

Abstract

PURPOSE:To improve the efficiency of data processing by checking read error every data read in the unit of blocks to quicken the processing in case of a data error. CONSTITUTION:In case of readout of comparatively long data stored separately in plural blocks, the data is read in the unit of blocks, the read error is checked for each block data and readout error information is generated by the result of check. That is, write data longer than a prescribed length or over among those given given via a serial I/04 is blocked into plural numbers and sent to a BCC (Block check code) arithmetic section 5, which executes arithmetic operation with respect to each block data and a BCC is added. Then the data added with the BCC is written in a data memory 7 via a write/read control section 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory error checking method employed in an IC card system or the like.

[Prior Art and Its Problems] In recent years, it has become known as the cashless era, and by using cards issued by credit card companies, it has become possible to purchase products without having to handle cash.

Conventionally, cards used include plastic cards, embossed cards, and magnetic striped cards, but these cards are easy to forge due to their structure, so unauthorized use has become a problem.

Therefore, in order to solve this problem, information cards, so-called IC cards, have been developed that incorporate an IC circuit that stores a PIN number inside the card so that the PIN number cannot be read easily from the outside. An IC card system that combines such an IC card and a terminal has been developed.

By the way, in such an IC card system, when reading data such as transactions from the memory in the IC card with the IC card installed in the terminal,
If the read data at this time is long as a single block, the data is divided into a plurality of blocks and sent. In this case, whether or not the data is correct is checked by adding a check code to the last block of data in a series of data.

However, according to this method of adding a check code to the end of data, even if so-called garbled data occurs in the card memory in the middle of data,
It will not be known that there is a memory error until all the data has been sent, and not only will all the data read out over time r1 be wasted, but the terminal side will not be able to perform any data processing during this time. However, there was a drawback that the efficiency of such data processing was significantly reduced.

[Objective of the Invention] The present invention has been made in view of the above circumstances, and provides a memory error checking method that can check errors for each data read in blocks and improve the efficiency of data processing. The purpose is to provide.

[Summary of the Invention] According to the memory error checking method according to the present invention,
When reading relatively long data that is stored in multiple blocks, such data is read in blocks, and read errors are checked for each block of data, and read error information is generated based on the results of this check. It looks like this.

[Embodiments of the invention] Hereinafter, one practical example of this invention will be explained with reference to the drawings.

FIG. 1 shows the circuit configuration of an IC card used in the same embodiment. In the figure, 1 is a system bus, and this system bus 1 includes a system program storage section 2, a working RAM 3, a serial l104, and a BCC calculation section 5.
is connected.

The system program storage unit 2 stores various system programs. The working RAM 3 is designed to store data provided from outside the card and various processing data within the card. Serial l104 is I1
Data is exchanged with a terminal (not shown) via the 0 terminal.

Of the write data given via the serial l104, data that is longer than a predetermined length is divided into multiple blocks and sent to the BCC.
It is sent to the calculation section 5. The BCC calculation unit 5 performs calculations for each block data and adds a BCC (block check code). The data to which the BCC has been added in this way is written to the data memory 7 via the write/success control section 6. Here, data memory 7 contains EE.
PROM (Electrical Erasable
Programmable ROM) or E
PROM (Erasable Pr.

grammable ROM) is used.

The data read from the data memory 7 is given to the comparator 8 via the write/read control unit 6, and
The signal is sent to the C calculation section 5. The BCG calculation unit 5 executes a BCC calculation on data assuming a state in which no BCC is added, and writes this result into the latch 51 and provides it to the comparator 8. The comparison result from the comparator 8 is then provided to the control section 9.

The control section 9 outputs operation commands to each circuit according to the data and operation state given via the serial I104, and also instructs output of correct/incorrect information of the read data according to the comparison result of the comparator 8.

Note that when the IC card thus constructed is attached to a terminal (not shown), a reset signal Re is sent from the terminal.
The 5et1 system clock CLOCK is supplied, the ccN source and the vpp power are supplied, and the ground IGND is connected. Here, Vcci! The power source is *i for system driving, and vpp is a power source for writing to the data memory 7.

Next, the operation of the embodiment configured as described above will be explained.

In this case, when writing data to the IC card, data that is longer than a predetermined length is divided into multiple blocks, and a BCC is added to each block by calculation in the BCC calculation unit 5. The data is written into the data memory 7 via the output control section 6.

In this state, data reading is performed, but in this case,
First, as shown in the flowchart of FIG. 2, a command to read specified data is sent from the terminal. This read command consists of 7 bytes as shown in FIG.
)' rcODJ Referenor REF1, REF2J
, inspection code rCHKJ. Here, r3AJ is used as the start code rsRAJ, for example. Also, the length rLNGJ is from rcLsJ to rcHK
The inspection code rcHKJ is “LN
It represents the transmission inspection code from GJ to before rcl-IKJ.

In step A1, the IC card reads the first block data from the data memory 7 based on the contents of the read command. Then proceed to step 2.

In this step A2, a BCC check is performed.

In this case, the data read from the data memory 7 according to the command from the control section 9 is given to the comparator 8 via the write/read control section 6, and is also sent to the BCC calculation section 5 at the same time.

The BCC calculation unit 5 calculates BC for data excluding BCC.
The G operation is executed and the result of this operation is written into the latch 51.

The contents of the latch 51 are then applied to the comparator 8 and compared with the BCC data directly applied from the data memory 7.

The comparison result of this comparator 8 is given to the control section 9. In this case, if there is no error in the reading from the data memory 7, the comparison by the comparator 8 will result in a match; on the other hand, if there is an error in the reading from the data memory 7, the comparison by the comparator 8 will result in a mismatch.

Here, if the comparison by the comparator 8 matches and it is determined that the BCC check is OK, the control unit 9 commands the BC
Block data to which information indicating C check rOKJ is added is returned to the terminal side. The return data in this case is the start code rSR, as shown in FIG. 3(b).
BJ, rLNGJ representing the message length, data rD
It consists of ATAJ, "BCC", and inspection code rCHKJ. Here, the start code rsRBJ is BCG
For example, rC5J is used as the check "OK" information. Furthermore, r8ccJ is BCC data used for BCC calculation on the IC card.

When such block data is sent to the terminal,
Next, a continuation command is sent from the terminal. This continuation command has almost the same content as the read command described in FIG. 3 (a>).

Then, in the IC card, block data is read out from the data memory 7 based on the contents of the continuation command in step A3, and in step A4, the block data is read out from the data memory 7 based on the contents of the continuation command.
A CC check is performed.

In this case, if the BCC check rOKJ is determined here as well, the block data to which the information "C5" indicating that the BCC check is "OK" is added is returned to the terminal in the same manner as described above.

Thereafter, in the same way, BC is set every time each block data is read.
A C check is executed, and if there is no error, the block data with "C5" added will be sent back to the terminal.

However, if an error occurs in reading data from the data memory 7 in step A3, B in step A4
In the CC check, it is determined that the data successively output from the data memory 7 and the data on which the BCC calculation was performed in the 8CG calculation unit 5 do not match. Then, this time the control section 9
In response to this command, block data to which information indicating BCG check rNGJ is added is returned to the terminal side. The returned data in this case is the same as that shown in FIG. 3(b) described above, but the start code rsRBJ is BCC check rNGJ information, and for example, "C6" is used.

In response to this, the terminal cancels the output of subsequent continuation commands and stops reading data from the IC card.

Therefore, by doing so, by checking read errors for each data read in blocks, it is possible to immediately identify data in a block in which an error has occurred. This makes it possible to immediately take the next steps, such as using normal block data as is and rereading the block data where an error occurred, and taking action in the event of a data error. It can be done quickly, and the efficiency of a series of data processing can be dramatically increased.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

For example, in the above embodiment, the BC for each block data
As rNGJ information of C check, start code rs
RBJ was used, but as shown in Figure 4(a), the most significant bit of rLNGJ, which represents the length of the message following the start code rsRBJ, is used, and "1" is used here.
” may be displayed. In addition, if such data is not to be returned, the process may be interrupted when an error occurs, and the error status may be returned to the terminal as shown in FIG. 4(b).

[Effects of the Invention] According to the present invention, it is possible to check read errors for each data read in blocks, so that it is possible to promptly take action in the event of a data error, and to improve the efficiency of data processing. A memory error checking method can be provided.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is a flow chart for explaining the operation of the embodiment, and Fig. 3 is a data read command and return command used in the embodiment. FIG. 4 is a configuration diagram for explaining returned data used in another embodiment of the present invention. 3... Working RAM, 5... BCC calculation section, 5
DESCRIPTION OF SYMBOLS 1... Latch, 7... Data memory, 8... Comparator, 9... Control part. Applicant Casio Computer Co., Ltd. (a) (b) Figure 3 (a) (b) Figure 4

Claims (1)

[Claims] a storage means for storing data divided into multiple blocks;
The present invention is equipped with a checking means for reading the data stored in the storage means block by block and checking for read errors for each block of data, and an error information generating means for generating read error information based on the check result of the checking means. Features a memory error checking method.