JPS63165940U - - Google Patents
Info
- Publication number
- JPS63165940U JPS63165940U JP5897487U JP5897487U JPS63165940U JP S63165940 U JPS63165940 U JP S63165940U JP 5897487 U JP5897487 U JP 5897487U JP 5897487 U JP5897487 U JP 5897487U JP S63165940 U JPS63165940 U JP S63165940U
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- transmission line
- line
- switching state
- terminal connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims description 33
- 238000001514 detection method Methods 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims 3
- 239000003990 capacitor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Description
第１図は本考案の一実施例のデータ伝送システ
ムの要部構成ブロツク図、第２図はＥＣＵにおけ
る切換状態検出回路の一例の回路図、第３図はＲ
Ｓにおける切換状態検出回路の一例の回路図、第
４図は第２図及び第３図に示す切換状態検出回路
の各部の信号のタイムチヤート、第５図は第１図
に示すシステムの作動を説明するタイムチヤート
である。
（符号の説明）、１……第１伝送ライン、２…
…第２伝送ライン、３……基準ライン、１０，１
０′……ＥＣＵ、１１……第１の伝送端子、１２
……第２の伝送端子、１３……基準端子、１４…
…平衡伝送レシーバ、１５……平衡伝送トランス
ミツタ、１６，１７……ラインスイツチ、１８…
…切換状態検出回路、２０……ＲＳ、２１……受
信端子、２２……送信端子、２３……基準端子、
２４……ラインレシーバ、２５……ラインドライ
バ、２６……ラインスイツチ、２７……切換状態
検出回路、３０……ＭＳ、３１……第１の接続端
子、３２……第２の接続端子、３３……基準端子
、３４……ラインドライバ、３５……ラインレシ
ーバ、３７……切換状態送出用ラインドライバ、
３６，３８……ラインスイツチ、５５……フリツ
プフロツプ、５６……リセツトタイマー、５７…
…ノアゲート、５８……タイマー。
Fig. 1 is a block diagram of the main part of a data transmission system according to an embodiment of the present invention, Fig. 2 is a circuit diagram of an example of a switching state detection circuit in an ECU, and Fig. 3 is a circuit diagram of an example of a switching state detection circuit in an ECU.
FIG. 4 is a circuit diagram of an example of the switching state detection circuit in S, FIG. 4 is a time chart of signals of each part of the switching state detection circuit shown in FIGS. 2 and 3, and FIG. 5 is a diagram showing the operation of the system shown in FIG. 1. This is a time chart to explain. (Explanation of symbols), 1...first transmission line, 2...
...Second transmission line, 3...Reference line, 10,1
0'...ECU, 11...First transmission terminal, 12
...Second transmission terminal, 13...Reference terminal, 14...
...Balanced transmission receiver, 15...Balanced transmission transmitter, 16, 17... Line switch, 18...
...Switching state detection circuit, 20...RS, 21...Reception terminal, 22...Transmission terminal, 23...Reference terminal,
24... Line receiver, 25... Line driver, 26... Line switch, 27... Switching state detection circuit, 30... MS, 31... First connection terminal, 32... Second connection terminal, 33 ...Reference terminal, 34...Line driver, 35...Line receiver, 37...Line driver for switching state transmission,
36, 38...Line switch, 55...Flip-flop, 56...Reset timer, 57...
...Noah Gate, 58...Timer.
Claims (1)
、基準ラインとを有する伝送ライン、 (b) 前記第１伝送ラインに接続される第１の
伝送端子と、前記第２伝送ラインに接続される第
２の伝送端子と、前記第１及び／又は第２伝送ラ
インが共に「ロー」となる切換状態を検出する切
換状態検出手段と、その切換状態を検出すると平
衡通信機能をマスクする通信マスク手段と、前記
基準ラインに接続される基準端子とを有する平衡
伝送局、 (c) 前記第１伝送ラインに接続される受信端
子と、前記第２伝送ラインに接続される送信端子
と、前記第１及び／又は第２伝送ラインが共に「
ロー」となる切換状態を検出する切換状態検出手
段と、その切換状態を検出するまでは不平衡通信
機能をマスクする通信マスク手段と、前記基準ラ
インに接続される基準端子とを有する不平衡伝送
リモート局、 および、 (d) 前記第１伝送ラインに接続される第１の
接続端子と、前記第２伝送ラインに接続される第
２の接続端子と、前記第１及び／又は第２伝送ラ
インを共に「ロー」とし次いで「ハイ」としてか
ら前記不平衡伝送リモート局と不平衡伝送による
通信を行う不平衡伝送通信手段と、前記基準ライ
ンに接続される基準端子とを有する不平衡伝送マ
スタ局 を具備してなることを特徴とするデータ伝送シス
テム。 ２ 切換状態検出手段が、コレクタをワイアード
オア接続された一対のトランジスタと、そのコレ
クタと電源ラインの間に設置された抵抗と、前記
コレクタとグランドの間に設置されたコンデンサ
と、前記コレクタに入力が接続されたシユミツト
・トリガ回路とを具備してなり、第１伝送ライン
および第２伝送ラインがそれぞれ前記トランジス
タのベースに接続され、前記シユミツト・トリガ
回路の出力が切換状態検出出力となる実用新案登
録請求の範囲第１項に記載のデータ伝送システム
。[Claims for Utility Model Registration] 1. (a) A transmission line having a first transmission line, a second transmission line, and a reference line; (b) A first transmission terminal connected to the first transmission line; , a switching state detection means for detecting a switching state in which a second transmission terminal connected to the second transmission line and the first and/or second transmission line are both "low"; and detecting the switching state. (c) a balanced transmission station having communication mask means for masking a balanced communication function; and a reference terminal connected to the reference line; (c) a reception terminal connected to the first transmission line; The transmission terminal to be connected and the first and/or second transmission line are both "
unbalanced transmission comprising switching state detection means for detecting a switching state of "low"; communication masking means for masking an unbalanced communication function until the switching state is detected; and a reference terminal connected to the reference line. a remote station, and (d) a first connection terminal connected to the first transmission line, a second connection terminal connected to the second transmission line, and the first and/or second transmission line. an unbalanced transmission master station having an unbalanced transmission communication means for communicating with the unbalanced transmission remote station by unbalanced transmission after setting both to "low" and then "high"; and a reference terminal connected to the reference line. A data transmission system comprising: 2. The switching state detection means includes a pair of transistors whose collectors are wire-OR connected, a resistor installed between the collector and the power supply line, a capacitor installed between the collector and ground, and an input to the collector. a Schmitt trigger circuit connected to the transistor, a first transmission line and a second transmission line are each connected to the base of the transistor, and the output of the Schmitt trigger circuit is a switching state detection output. A data transmission system according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5897487U JPH0537563Y2 (en) | 1987-04-17 | 1987-04-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5897487U JPH0537563Y2 (en) | 1987-04-17 | 1987-04-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63165940U true JPS63165940U (en) | 1988-10-28 |
| JPH0537563Y2 JPH0537563Y2 (en) | 1993-09-22 |
Family
ID=30890036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5897487U Expired - Lifetime JPH0537563Y2 (en) | 1987-04-17 | 1987-04-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537563Y2 (en) |
-
1987
- 1987-04-17 JP JP5897487U patent/JPH0537563Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0537563Y2 (en) | 1993-09-22 |
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