JPS6183358U - - Google Patents
Info
- Publication number
- JPS6183358U JPS6183358U JP16796684U JP16796684U JPS6183358U JP S6183358 U JPS6183358 U JP S6183358U JP 16796684 U JP16796684 U JP 16796684U JP 16796684 U JP16796684 U JP 16796684U JP S6183358 U JPS6183358 U JP S6183358U
- Authority
- JP
- Japan
- Prior art keywords
- data transmission
- reception processing
- power supply
- processing unit
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Power Sources (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は従来例のデータ送受信装置の原理構成
図、第２図は従来例の一変形例を示す原理構成図
、第３図は本考案のデータ送受信装置の原理構成
図、第４図ａは本考案に用いた半導体スイツチ回
路図、第４図ｂは本考案の半導体スイツチ回路の
等価回路図でる。
３，１３…リセツト回路、３０…データ伝送装
置、３１…データ端末装置、３２，３３…半導体
スイツチ回路。
FIG. 1 is a diagram showing the principle configuration of a conventional data transmitting/receiving device, FIG. 2 is a diagram showing a modification of the conventional example, FIG. 3 is a diagram showing the principle configuration of a data transmitting/receiving device according to the present invention, and FIG. 4 a 4 is a circuit diagram of the semiconductor switch used in the present invention, and FIG. 4b is an equivalent circuit diagram of the semiconductor switch circuit of the present invention. 3, 13...Reset circuit, 30...Data transmission device, 31...Data terminal device, 32, 33...Semiconductor switch circuit.
Claims (1)
部通信用バツフア、前記中央演算ユニツトヘリセ
ツト信号を送るリセツト回路および駆動電源、電
源投入用スイツチとからなるデータ送受信処理装
置において、干渉電流流れ込み防止用半導体スイ
ツチ回路を具備したことを特徴とするデータ送受
信処理装置。 In a data transmission/reception processing device consisting of a central processing unit for data transmission/reception processing, a buffer for external communication, a reset circuit for sending a reset signal to the central processing unit, a driving power supply, and a power supply switch, a semiconductor switch circuit for preventing interference current flow is provided. A data transmission/reception processing device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16796684U JPS6183358U (en) | 1984-11-07 | 1984-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16796684U JPS6183358U (en) | 1984-11-07 | 1984-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183358U true JPS6183358U (en) | 1986-06-02 |
Family
ID=30725751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16796684U Pending JPS6183358U (en) | 1984-11-07 | 1984-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183358U (en) |
-
1984
- 1984-11-07 JP JP16796684U patent/JPS6183358U/ja active Pending
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