JPS63165930U - - Google Patents
Info
- Publication number
- JPS63165930U JPS63165930U JP5883187U JP5883187U JPS63165930U JP S63165930 U JPS63165930 U JP S63165930U JP 5883187 U JP5883187 U JP 5883187U JP 5883187 U JP5883187 U JP 5883187U JP S63165930 U JPS63165930 U JP S63165930U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pll
- voltage limiting
- vco
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は従来のＰＬＬ回路を示す回路図、第３図及
び第４図は従来のＰＬＬ回路の説明に供する為の
特性図、第５図は第１図の具体回路例を示す回路
図、及び第６図は第５図の説明に供する為の特性
図である。
１……位相比較回路、２……ローパスフイルタ
、３……ＶＣＯ、７……アンロツク検出回路、８
……電圧制限回路、９……スイツチ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional PLL circuit, and FIGS. 3 and 4 are characteristic diagrams for explaining the conventional PLL circuit. FIG. 5 is a circuit diagram showing a specific example of the circuit shown in FIG. 1, and FIG. 6 is a characteristic diagram for explaining FIG. 1... Phase comparison circuit, 2... Low pass filter, 3... VCO, 7... Unlock detection circuit, 8
...Voltage limiting circuit, 9...Switch.
Claims (1)
備えるＰＬＬ回路において、前記ＶＣＯの制御端
子に接続される電圧制限回路と、前記ＰＬＬ回路
のアンロツク状態を検出するアンロツク検出回路
とを設け前記ＰＬＬ回路のアンロツク時に前記電
圧制限回路を動作させたことを特徴とするＰＬＬ
回路。 A PLL circuit including a phase comparison circuit, a low-pass filter, and a VCO includes a voltage limiting circuit connected to a control terminal of the VCO and an unlock detection circuit for detecting an unlocked state of the PLL circuit. PLL characterized by operating a voltage limiting circuit
circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5883187U JPS63165930U (en) | 1987-04-17 | 1987-04-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5883187U JPS63165930U (en) | 1987-04-17 | 1987-04-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63165930U true JPS63165930U (en) | 1988-10-28 |
Family
ID=30889758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5883187U Pending JPS63165930U (en) | 1987-04-17 | 1987-04-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63165930U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59210731A (en) * | 1983-05-13 | 1984-11-29 | Iwatsu Electric Co Ltd | Phase-locked loop circuit device |
-
1987
- 1987-04-17 JP JP5883187U patent/JPS63165930U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59210731A (en) * | 1983-05-13 | 1984-11-29 | Iwatsu Electric Co Ltd | Phase-locked loop circuit device |