JPS63164738A - Network state supervising circuit - Google Patents

Network state supervising circuit

Info

Publication number
JPS63164738A
JPS63164738A JP61314694A JP31469486A JPS63164738A JP S63164738 A JPS63164738 A JP S63164738A JP 61314694 A JP61314694 A JP 61314694A JP 31469486 A JP31469486 A JP 31469486A JP S63164738 A JPS63164738 A JP S63164738A
Authority
JP
Japan
Prior art keywords
path
node
map
switching state
route
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61314694A
Other languages
Japanese (ja)
Inventor
Shinjiro Tsumura
津村 信二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61314694A priority Critical patent/JPS63164738A/en
Publication of JPS63164738A publication Critical patent/JPS63164738A/en
Pending legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To relieve the load of the maintenance personnel by applying retrieval processing depending on the switching state of a node and a path map so as to discriminate the propriety of use of the systematic path thereby raising an alarm in case of a fault. CONSTITUTION:A switching state memory 14 of nodes 5, 6 inputs the switching state of the nodes 5, 6 and stores it and a retrieval circuit 15 starts the path retrieval of the pass map 12 taking this input as a chance. If the path is faulty in terms of system, a node (N1) in a path 1 (P1) is read to reference the node N1 of a node map 13. In this case, since the content of the switching state memory 14 is OFF, a path 2 (P2) is selected and a node (N2) of the path map 12 is read again to reference the N2 of the node map 13. Since the content of the switching state memory 14 is ON in this case, a path 4' (P4') is referenced to read NG from the P4' of the path map 12, it is discriminated to be path fault in terms of system to raise an alarm output. Thus, it is not required for the maintenance personnel to supervise always the external display device and the load is relieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はネットワークの状態監視回路、特にシステム的
なパスの使用状態の可否を判断する監視回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a network status monitoring circuit, and more particularly to a monitoring circuit for determining whether or not a system path is in use.

〔従来の技術〕[Conventional technology]

従来、この種のネットワーク監視回路はノードの切替状
態を外部から入力して、この状態情報を外部表示器例え
ばCRTイメージ図形または文字等に表現して1対1に
表示出力していた。
Conventionally, this type of network monitoring circuit inputs the switching state of a node from the outside, expresses this state information on an external display, for example, a CRT image, or characters, and outputs it for display on a one-to-one basis.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のネットワーク監視回路はノードの切替状
態をありのままに外部表示器に表示しているだけで、シ
ステム的なパスの使用状態の可否までは判断しない、従
ってシステム的に使用してはならない経路が使用されて
も警告を発することができないため、常に保守者が外部
表示器を監視していなければならないという欠点があっ
た。
The conventional network monitoring circuit described above only displays the switching status of nodes as is on an external display, but does not determine whether or not the system-wide path usage status is available.Therefore, there are routes that should not be used systematically. Since it is not possible to issue a warning even if the external display is used, there is a drawback that maintenance personnel must constantly monitor the external display.

本発明の目的は前記問題点を解消するネットワーク状態
監視回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a network status monitoring circuit that solves the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はネットワークのパスを流れる信号の経路を決定
するネットワークのノードの切替状態を記憶し各ノード
に1対1に対応したノード切替状態メモリと、入口のパ
スから出口のパスまでのすべての経路を表現しシステム
的に使用可と使用不可とのパスの区別をした識別マーク
を出口のパスに付与した経路マツプと、前記ノード切替
状態メモリに外部から切替状態が入力する度に前記ノー
ド切替状態メモリを参照しつつ入口のパスから前記経路
マツプの出口のパスまで辿り、前記識別マークによりシ
ステム的なパスの使用状態の可否を判断し外部表示器等
に出力する検索回路とを有することを特徴とするネット
ワーク状態監視回路である。
The present invention includes a node switching state memory that stores the switching state of network nodes that determines the route of a signal flowing through a network path, and has a one-to-one correspondence with each node; A route map in which an identification mark is added to the exit path to express the system and distinguish between usable and unusable paths. It is characterized by having a search circuit that traces from the entrance path to the exit path of the route map while referring to the memory, determines whether or not the path can be used systematically based on the identification mark, and outputs the result to an external display device or the like. This is a network status monitoring circuit.

〔実施例〕〔Example〕

以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図において、本発明はネットワークのパスを流れる
信号の経路を決定するネットワークのノードの切替状態
を記憶し各ノードに1対1に対応したノード切替状態メ
モリ14と、入口のパスから出口のパスまでのすべての
経路を表現しシステム的に絶対通過してはならないパス
と通過してよいパスの区別をした識別マークを出口のパ
スに付与した経路マツプ11と、前記ノード切替状態メ
モリ14に外部から切替状態が入力する度に前記ノード
切替状態メモリ14を参照しつつ入口のパスから前記経
路マツプの出口のパスまで辿り、前記識別マークにより
システム的なパスの使用状態の可否を判断し外部表示器
等に出力する検索回路15とを有するものである。12
はパスマツプ、13はノードマツプを示す。経路マツプ
11は第2図のネットワークの経路を示したものである
。経路マツプ11はパスからノードの参照指示を示すバ
スマツプ12とノードからパスの参照指示を示すノード
マツプ13で構成する。ノードの切替状態メモ1月4は
第2図のノードの切替状態を入力して蓄積する。この入
力を契機として検索回路15はバスマツプ12の経路検
索のスタートとしてパス1をPlから検索を開始する。
In FIG. 1, the present invention includes a node switching state memory 14 that stores the switching state of the network nodes that determines the route of the signal flowing through the network path, and has a one-to-one correspondence with each node; A route map 11 representing all routes up to the path and adding identification marks to exit paths to distinguish between paths that must not be passed and paths that can be passed, and the node switching state memory 14. Every time a switching state is input from the outside, the path is traced from the entrance path to the exit path of the route map while referring to the node switching state memory 14, and the system determines whether or not the path is in use based on the identification mark. The search circuit 15 includes a search circuit 15 for outputting to a display device or the like. 12
indicates a path map, and 13 indicates a node map. A route map 11 shows the route of the network shown in FIG. The route map 11 is composed of a bus map 12 indicating reference instructions from a path to a node, and a node map 13 indicating reference instructions from a node to a path. Node switching status memo January 4 inputs and stores the node switching status shown in FIG. In response to this input, the search circuit 15 starts searching for a route in the bus map 12 from Pl.

第2図はパス1〜4およびノード5,6で構成されたネ
ットワークを示す。第3図、第4図はノード5,6各々
の切替状態を示し、7,9がOFF状態、8゜10がO
N状態をそれぞれ表わす。
FIG. 2 shows a network made up of paths 1-4 and nodes 5 and 6. Figures 3 and 4 show the switching states of nodes 5 and 6, with nodes 7 and 9 in the OFF state, and 8° and 10 in the OFF state.
N states are respectively represented.

システム・に  正常 5 な ム パス1 (PI)内のノード1 (Nl)を読出しノー
ドマツプ13のN1を参照する。この場合、切替状態メ
モリ14の内容がOFFであるため、パス2 (P2)
を選択する。このPiから再びバスマツプ12のノード
2(N2)を読出しノードマツプ13のN2を参照する
。この時切替状態メモ音用4の内容がOFF ’である
ため、パス4 (P4)を参照しバスマツプ12のP4
からOKを読出しシステム的に経路正常と判断する。
Read node 1 (Nl) in path 1 (PI) that is normal in the system and refer to N1 in node map 13. In this case, since the contents of the switching state memory 14 are OFF, the path 2 (P2)
Select. From this Pi, node 2 (N2) of the bus map 12 is read again and N2 of the node map 13 is referred to. At this time, since the contents of switching status memo sound 4 are OFF', refer to path 4 (P4) and select P4 of bus map 12.
The system reads OK from the path and determines that the route is normal.

システム的に経    、6図)な場合バス1 (Pi
)内のノード1 (Nl)を読出しノードマツプ13の
Nlを参照する。この場合切替状態メモリ14の内容が
OFFであるため、パス2 (P2)を選択する。この
P2から再びバスマツプ12のノード2 (N2)を読
出しノードマツプ13のN2を参照する。この時切替状
態メモリ14の内容がONであるため、パス4′(P4
’)を参照しバスマツプ12のP4’からNGを読出し
システム的に経路異常と判断し、警告出力を行う。
Systematically, if bus 1 (Pi
) is read out and Nl in the node map 13 is referred to. In this case, since the contents of the switching state memory 14 are OFF, path 2 (P2) is selected. From this P2, node 2 (N2) of the bus map 12 is read again and N2 of the node map 13 is referred to. At this time, since the contents of the switching state memory 14 are ON, the path 4' (P4
), reads NG from P4' of the bus map 12, determines that the route is abnormal from a system standpoint, and outputs a warning.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はノードの切替状態と経路マ
ツプから検索処理することによりシステム的な経路の使
用可否を判断し、異常な場合警告を発することができる
ため、保守者の負担を軽減する効果がある。
As explained above, the present invention can determine the usability of a systematic route by performing a search process based on the node switching status and the route map, and can issue a warning in the event of an abnormality, thereby reducing the burden on maintenance staff. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
ネットワーク構成を示す図、第3図、第4図はノードの
各々の切替状態を示す図、第5図はシステム的に経路正
常な場合の一例を示す図、第6図はシステム的に経路異
常な場合の一例を示す図である。 11・・・経路マツプ   12・・・バスマツプ13
・・・ノードマツプ  14・・・ノード切替状態メモ
リ15・・・検索回路
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the network configuration, FIGS. 3 and 4 are diagrams showing the switching states of each node, and FIG. 5 is a diagram showing the system configuration. FIG. 6 is a diagram showing an example of a case where the route is normal, and FIG. 6 is a diagram showing an example of a case where the route is systemically abnormal. 11... Route map 12... Bus map 13
... Node map 14 ... Node switching state memory 15 ... Search circuit

Claims (1)

【特許請求の範囲】[Claims] (1)ネットワークのパスを流れる信号の経路を決定す
るネットワークのノードの切替状態を記憶し各ノードに
1対1に対応したノード切替状態メモリと、入口のパス
から出口のパスまでのすべての経路を表現しシステム的
に使用可と使用不可とのパスの区別をした識別マークを
出口のパスに付与した経路マップと、前記ノード切替状
態メモリに外部から切替状態が入力する度に前記ノード
切替状態メモリを参照しつつ入口のパスから前記経路マ
ップの出口のパスまで辿り、前記識別マークによりシス
テム的なパスの使用状態の可否を判断し外部表示器等に
出力する検索回路とを有することを特徴とするネットワ
ーク状態監視回路。
(1) A node switching state memory that stores the switching states of network nodes and corresponds one-to-one to each node, which determines the route of signals flowing through the network path, and all routes from the entrance path to the exit path. A route map in which an identification mark is given to an exit path to express the system and distinguish between usable and unusable paths; It is characterized by having a search circuit that traces from the entrance path to the exit path of the route map while referring to the memory, determines whether or not the path can be used systematically based on the identification mark, and outputs the result to an external display device or the like. network status monitoring circuit.
JP61314694A 1986-12-26 1986-12-26 Network state supervising circuit Pending JPS63164738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61314694A JPS63164738A (en) 1986-12-26 1986-12-26 Network state supervising circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61314694A JPS63164738A (en) 1986-12-26 1986-12-26 Network state supervising circuit

Publications (1)

Publication Number Publication Date
JPS63164738A true JPS63164738A (en) 1988-07-08

Family

ID=18056422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61314694A Pending JPS63164738A (en) 1986-12-26 1986-12-26 Network state supervising circuit

Country Status (1)

Country Link
JP (1) JPS63164738A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210132822A (en) 2020-04-28 2021-11-05 두산공작기계 주식회사 Spindle head device of machine tool with laser powder material laminator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210132822A (en) 2020-04-28 2021-11-05 두산공작기계 주식회사 Spindle head device of machine tool with laser powder material laminator

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