JPS63164609A - Level converting circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit with less temperature dependancy and stable operation by cancelling the temperature characteristics of forward voltage of a diode or a transistor (TR) used for a differential amplifier stage and a level shift stage by a bias circuit using a forward voltage of a TR of a diode. CONSTITUTION:Resistors R1, R2 connected to collectors of NPN TRs Q1, Q2 forming a differential pair are connected to a power supply VCC via the emitter- collector path of an NPN TR Q9 and the base of the NPN TR Q9 is connected to the power supply VCC via a constant current source I06 and connected to an earth terminal via the emitter-collector path of a PNP TR Q10 and three diodes D6, D7 D8 connected in series. Since the shape of the diodes D1-D4 and D6-D8 and the TRs Q3, Q4, Q9 and Q10 is matched, the level shift stage comprising the NPN TRs Q3, Q4 and the diodes D1-D4 is operated very stably with less temperature dependancy.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit with reduced temperature dependence.

(Conventional example) Figure 3 shows a conventional emitter follower type level conversion circuit, including NPN) transistors Q1, Q2, and resistors RI and R.
The output signal of the differential amplifier consisting of t and constant current source to+ is NPN) transistor Q, % diode DI % ORS
and a level shift stage consisting of a constant current source 11H, and an NPN
) The level is shifted by a level shift stage consisting of a transistor Q4, diodes D3 and D4, and a constant current source 103.

That is, the base of the transistor Q2 is biased to a predetermined voltage by voltage dividing resistors R1 and R4 connected between the power supply Vcc and the ground terminal, while the transistor Q1 is biased to a predetermined voltage by the voltage dividing resistors R1 and R4 connected between the power supply Vcc and the ground terminal.
It is biased to a predetermined voltage by a voltage dividing resistor Rs, R, connected between The levels are converted by an amplifier and output as signals having opposite phases to the bases of transistors Qs and Qa.

One signal is the base-emitter voltage V0. of transistor Q. and the respective forward voltages V of the diode DISDt
The level is shifted by 1, 15vDffi and output to the output terminal 0UTI. The other signal is the transistor Q
Base-emitter voltage of 4 ■. 4 and diode D+,
The level is shifted by the respective forward voltages v0 and D4 of Dm and output to the output terminal 0UT2.

Such a level conversion circuit is used as a control circuit for the sample and hold circuit shown in FIG.

In the figure, an NPN terminal has input terminals INI and IN2 connected to the output terminals 0UTI and 0UT2 in FIG. 4, respectively, and whose base is connected to the input terminals INI and IN2.
) The emitters of transistors Qs and Q are constant current sources ■. ,
is connected to the ground terminal via. Between the collectors of the NPN) transistors Q, , Q, an NPNl-transistor Q, whose base and emitter are connected in series, is provided. The base of the transistor Q is connected to the emitter of the NPN transistor Ql and the constant current source 111 via the resistor R1.
4 and the signal V to be sampled and held at the signal input terminal connected to the base of the transistor Q-,
&, is now supplied.

The emitter of the (NPN) transistor Q7 is connected to a ground terminal via a hold capacitor C, and the hold voltage generated across the hold capacitor C is outputted via an output buffer amplifier BA.

When a rectangular signal is applied to the input terminal IN of the circuit shown in FIG. 3, clock signals with voltage amplitudes having mutually opposite phases are generated at the output terminals 0UTI and 0UT2. These clock signals are supplied to the input terminals INI and IN2 of the sample-and-hold circuit shown in FIG. Transistor Q is off,
When transistor Q is off, it holds the charge accumulated in capacitor C.

If a clock signal with a large amplitude or a high DC level is applied to the transistor QsSQ& of the sample-and-hold circuit shown in FIG. In order to prevent this problem, a level conversion circuit shown in FIG.
The rectangular signal supplied to N is level-converted into a clock signal having an appropriate logic amplitude and an appropriate DC level.

In this way, the level conversion circuit is an extremely effective means, especially in the case of a direct-coupled circuit or a circuit that operates with a low voltage power supply.

(Problems to be Solved by the Invention) However, in such conventional level conversion circuits, the diodes, etc. for level shifting have temperature dependence, so the DC level of the signal after level conversion is It fluctuated depending on the temperature, making it impossible to perform accurate level conversion.

In the circuit shown in FIG. 3, transistor Q3 and diode D1. ．． D! The temperature characteristics of the forward voltage of transistor Q4, diode 03, and Dm are approximately -6 mV.
/'C, and for example, in an integrated circuit used at -25°C to 125°C, a DC bias fluctuation of approximately IV occurs. Furthermore, since this DC bias variation shifts toward the power supply voltage side, a problem arises in that the dynamic range becomes smaller, which is an extremely serious drawback especially in circuits that operate on a low voltage power supply.

Furthermore, the temperature dependence of the front stage side, that is, the differential amplifier, is also a problem. Figure 5 shows the transistors Q+ and Q in Figure 3.
In order to operate the circuit stably, the base potential V□ of the transistor Q2 is changed to the base potential of the other transistor Q (contact point Approximately 500 mV more than the potential of
When a signal is applied to the input terminal IN with a low setting, the differential pair Q
The threshold voltage Vtk for operating + -Qt changes as shown. At this time, transistors Q+, Qt
Since the base potential of V is constant regardless of temperature changes, the DC bias point also shifts depending on changes in the threshold voltage V,
As a result, the noise margin is reduced.

(Means for Solving the Problems) The present invention has been made in view of the above problems, and provides a level conversion circuit that has little temperature dependence and is suitable for operation with a low voltage power supply. The purpose is to To achieve this object, the present invention includes an amplification stage having a differential pair consisting of first and second transistors, an output signal from the amplification stage being supplied to the base, the collector being connected to the power supply, and the emitter being connected to the power supply. In a level shift circuit comprising a level shift stage having a transistor connected to an output terminal via one or more series-connected diodes, a DC bias of an output contact of the amplification stage is controlled by one or more diodes and or a first bias circuit that sets the temperature characteristic between the output terminal of the level shift stage and the base of the transistor equal to the temperature characteristic between the output terminal of the level shift stage and the base of the transistor by a forward voltage generated by the series connection of transistors;
An input terminal that supplies an input signal to the base of the transistor via an input diode, and a forward voltage of the diode and/or transistor changes the DC base bias potential of the first transistor to the DC base bias potential of the second transistor. a second bias circuit that sets the input diode to a higher potential by the forward voltage of the input diode;
The technical point is to reduce the temperature dependence of the level shift stage and differential amplification stage.

(Embodiment) An embodiment of the level conversion circuit according to the present invention will be described below with reference to FIG. In this figure, the same or corresponding parts as in FIG. 3 are given the same reference numerals.

To explain the difference with Fig. 3, the NPs forming the differential pair
N) Resistor R+ connected to the collector of transistor Q, Rx is connected to the power supply ycc through the emitter-collector path of NPN) transistor Q, and the base of NPN) transistor Q is a constant current source ■ . , through the power supply V
- and three diodes connected in series Dh-D? , D, and PNP transistor Q,. is connected to the ground terminal via the emitter-collector path.

The base of the PNP transistor Q+a is the output terminal 0UTl
, a reference bias voltage v5.0 for setting the DC bias of 0UT2, etc. is connected to the terminal that applies it.

The emitter of the diode Dh is an NPN) transistor Ql.
The base of the NPN transistor Q is connected to the base of the NPN transistor, the collector of the transistor Q is connected to the power supply Vcc, and the emitter is connected to the NPN transistor through the resistor R8.
PN) tJJE to the base of transistor Q1, NPN
The DC base bias of transistor Q is set. The emitter of diode D7 is NPN) transistor QI! The base of is connected, NPN) transistor QI!
The collector is connected to the power supply VCC, and the emitter is a constant current source]. ,
is connected to the ground terminal via the NPN transistor Q2 and to the base of the NPN transistor Q2.
DC base bias is set.

Here, the DC bias potential V1+ (potential of contact ■) of the base of the NPN transistor Q is the base-emitter voltage of the PNP transistor Qf, which is V*X+ and the diode D? , the forward voltage of DI is vl, ? , VeslNPN
) The base-emitter voltage of transistor QII is Vll!
II, if the voltage drop due to resistor R1 is V□, then Vm+-(Vmm+Vot+Vos) -(VIEll
+Vll)・・・・・・・・・・・・・・・(1), the DC bias potential Vat (corresponding to V□r in FIG. 3) at the base of one NPN transistor Q2 is N
PN) Langister Ql! The base-emitter voltage of VI
E1! Then, V+u= (Vm*+Vas)'Vmtr"""
(2) Therefore, the difference ΔV between the respective DC bias potentials is: ΔVm = Vm+ Vmt= VD? -Vll+
(VIEIIVmi+x) ・・・・・・・・・
・・・・・・・・・(3), and VOII"Vll
! I! Each transistor q, , Q1g so that
Since matching is achieved, the difference in DC bias potential Δvl
is set by the forward voltage V of the diode D7 and the voltage drop vlIll of the resistor R8, and the DC bias V of the NPN transistor Q1 is set to a potential higher by approximately 500 mV than the DC bias VSZ of the NPN transistor Q8. There is.

In addition, the DC bias potential V of output terminals 0UTI and 0UT2
. U□ and V6tl□ are set by the reference bias voltage V□ as described above. That is, if the potential of the base contact [F] of the transistor Q9 is VP%, and the forward voltage of the diode D6 is V□, then VP = Vmt + Voa + VB +
Vos "" (4) and further NPN transistor Q? , h , Qa, respectively, vllE9, Vmm3 s Vain-da4t-V
D+, Dt SO2-DaO) forward voltage is
If ll, vo, ■, 1, VO4, output terminal 0UT
I, 0UT2 DC bias potential V. 1lT1% vo
oy□ is Vout+-Vp (Vstw +v0
1 +Vo++Vox)・・・・・・・・・・・・・・・
...(5) Voutz=Vp (Vstq +
Vmtm +Voff+VaJ・・・・・・・・・・・・
......(6). Here, the diode D,
~D4 and Dh~D- and transistors Q1, Q4, Ql
,Q. Since matching is done for the shape of , substituting the above equation (4) into the above equations (5) and (6), Vooy+ 7 Vout*″vll………………(7
), therefore, NPN) transistors Q1, Q4
The level shift stage formed by the diodes D and D4 has little temperature dependence and operates extremely stably.

Next, the input threshold voltage v1 of the input terminal IN is set to a potential lower than the base bias V□ of the transistor Q by the forward voltage V□ of the diode D.

VIIIM ”'Vll vos ・・・・・・・・・
・・・・・・・・・・・・・・・・・・(8) Here, by substituting the above formula (1) into the above (8), vlI,, 4=
(v, , +vl, , +vD,) −(v, , , +V'
s) VDS = (Vmm Vmm) + (VD?+Vos)
-(V□11-■□)・・・・・・・・・・・・・・・
(9), and the diodes Dt, Ds, Ds and N
Matching is done so that the forward voltage and base-emitter voltage of the Q-th PN transistor are equal, so
The right side of the above (9) is (V□-V□). Therefore, the input signal applied to the input terminal IN is connected to the diode D,
is not affected by the temperature dependence of

FIG. 2 is a characteristic curve diagram showing voltage changes at appropriate contact points to show the temperature characteristics of the level conversion circuit having such a configuration. In addition, the figure shows that the input terminal IN is at the “■1” level (approximately 5
It shows the characteristics when a voltage of V) is applied, and the characteristic curve 'IIA
[F], ■, ■ are the voltages at the contacts shown in Figure 1, and the curve v0
is the DC base bias of the transistor Qt, the curve Vt&
1 and 2 respectively show the characteristics of the threshold voltages of the differential pair Q7 and Q2 with respect to the voltage level of the input signal applied to the input terminal IN.

As shown in the figure, the threshold value V□ is a diode D.

It is always constant because it is not affected by the temperature dependence of ΔV? The potential difference Δv0 between +, curve ■ and vo is always equal to temperature change (ΔV?+
−△V? Therefore, when the input is at the "■)" level, the base of the transistor Q is higher than the base of the transistor Qt by ΔVTl regardless of the temperature, and the noise margin is also improved. Furthermore, since the threshold value V is always constant, it is possible to obtain the effect that no phase shift of the input signal occurs during high-speed operation.

(Effects of the Invention) As explained above, according to the level conversion circuit of the present invention,
The temperature dependence of the forward voltage of the diodes and/or transistors used in the differential amplifier stage and level shift stage is canceled out by a bias circuit using the forward voltage of the transistors and/or diodes. It is possible to provide a level conversion circuit that operates stably with extremely low noise and has excellent noise tolerance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the level conversion circuit according to the present invention, FIG. 2 is a characteristic curve diagram showing the temperature characteristics of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional level conversion circuit. 4 is a circuit diagram showing a sample-and-hold circuit as an application example to which the circuit shown in FIG. 3 is applied, and FIG. 5 is a characteristic curve diagram showing the temperature characteristics of the circuit shown in FIG. 4. Q, ~Q+z:) transistor D, ~D,
=Diode R8-R1: Resistance 101-I0. : Constant current source 0UT1.0UT2 : Output terminal IN = Input terminal (3 idiots) ("C) Cow 4S 小 1〒艮'Auto゛ Monthly 1. Indication of the case 1986 ■ Particularly 1 Application No. 308768 2 Name of the invention Level conversion circuit name: (520) Fuji Photo Film Co., Ltd. 4, Agent Person 6, Subject of amendment: Column 7 of "Detailed explanation of the invention" in the specification column, Contents of amendment: "Detailed explanation of the invention" of the specification
Correct the column as follows. (1) Detail drawing, page 3, line 20, replace “1” in “Figure 4” with “
In Figure 3, it is corrected. (2) Correct "on" in the third line of page 5 to "off". (3) Correct "off" in the fourth and fifth lines of page 5 of the same circle to "on". (4) On page 6, line 9 of the same book, after “What are the properties of warm stone?”
Insert the sum (゛) in each case. (5) [Approximately 50011V
Correct J to approximately 700 mVJ.

Claims (1)

[Claims] An amplification stage having a differential pair consisting of first and second transistors; an output signal from the amplification stage is supplied to a base, a collector is connected to a power supply, and one or more emitters are connected to a power supply; In a level conversion circuit comprising a level shift stage having a transistor connected to an output terminal via series-connected diodes of a first bias circuit that sets equal temperature characteristics between the output terminal of the level shift stage and the base of the transistor by a forward voltage generated by the connection; and a base of the first transistor forming the differential pair. An input terminal that supplies an input signal via an input diode to the input terminal, and a forward voltage of the diode and/or transistor.
A second transistor that sets the DC base bias potential of the first transistor to a potential that is higher than the DC base bias potential of the second transistor by the forward voltage of the input diode.
A level conversion circuit characterized by comprising a bias circuit.