JP2018036348A - Display driver and semiconductor device - Google Patents

Abstract

PURPOSE: To provide a display driver and a semiconductor device capable of supplying a display drive voltage with suppressed distortion to a display device.CONSTITUTION: The display driver comprises: a bias voltage generating part generating a bias voltage; and a plurality of amplifiers individually amplifying each gradation voltage corresponding to a brightness level of each pixel and generating a plurality of display drive voltages. Each amplifier includes: an operational current generating part generating an operational current with amplitude corresponding to the bias voltage; a differential pair dividing the operational current into first and second currents at a voltage value ratio of the gradation voltage to the display drive voltage and outputting them to first and second lines, respectively; and an output part generating a display drive voltage on the basis of the voltage of the first line. Here, the bias voltage generating part has a source follower circuit including a transistor that receives at a gate end a bias set voltage for setting a voltage value of the bias voltage, and supplies a voltage of a source end to each of the plurality of amplifiers as a bias voltage.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a display driver that drives a display device according to a video signal and a semiconductor device in which the display driver is formed.

  For example, a liquid crystal display device that displays an image according to a video signal is provided with a liquid crystal display panel as a display device and a driver that drives a plurality of source lines of the display panel. The driver includes a plurality of decoders that individually convert a plurality of gradation data pieces for each pixel based on a video signal into analog gradation voltages, and amplify the gradation voltages with a gain of 1 to supply the source lines. A plurality of differential amplifier circuits (hereinafter referred to as amplifiers) (see, for example, Patent Document 1). Further, such a driver is provided with a bias circuit for generating a bias signal for setting an operating current flowing in each amplifier.

JP 2004-301946 A

  By the way, when the voltage value of the gradation voltage input to each amplifier transitions from a low state to a high voltage state suddenly decreasing, a noise is generated in which the voltage value of the bias signal temporarily increases due to this transition.

  Therefore, if a large number of amplifiers are simultaneously supplied with a gradation voltage that transitions from a low voltage to a high voltage state, the increase in the voltage value of the bias signal cannot be suppressed on the bias circuit side, and the output voltage of each amplifier is reduced. There was a problem of distortion.

  Therefore, the present invention suppresses the influence of noise generated in the bias signal and reduces waveform distortion even when a plurality of amplifiers are simultaneously supplied with a gradation voltage that transitions from a low voltage state to a high voltage state. An object is to provide a display driver and a semiconductor device capable of generating a suppressed display drive voltage.

  The display driver according to the present invention supplies a plurality of display drive voltages obtained by individually amplifying each gradation voltage having a voltage value corresponding to the luminance level of each pixel to a plurality of data lines of the display device. A display driver including a plurality of amplifiers, and having a bias voltage generation unit that generates a bias voltage, each of the plurality of amplifiers having a size corresponding to the first and second lines and the bias voltage An operating current generating unit configured to generate an operating current; and the first and second lines by dividing the operating current into first and second currents by a ratio of a voltage value between the grayscale voltage and the display driving voltage. Each of the differential pair and the output unit for generating the display driving voltage based on the voltage of the first line, wherein the bias voltage generating unit receives a bias setting voltage at the gate end, Before the voltage It includes a source follower circuit having a transistor for supplying said plurality of amplifiers each as a bias voltage.

The display driver according to the present invention also applies a plurality of display drive voltages obtained by individually amplifying each of the gradation voltages having a voltage value corresponding to the luminance level of each pixel to a plurality of data lines of the display device. A display driver including a plurality of amplifiers to be supplied, the display driver including a bias voltage generation unit that generates first and second bias voltages, wherein each of the plurality of amplifiers receives supply of a power supply voltage. A first bias transistor that generates a current having a magnitude corresponding to the bias voltage of the first bias transistor, and a second bias transistor that outputs the current generated by the first bias transistor as an operating current according to the second bias voltage. The operating current is divided into first and second currents by a bias transistor, first and second lines, and a ratio of voltage values of the grayscale voltage and the display driving voltage. A differential pair respectively sent to line, comprising an output unit for generating the display drive voltage based on a voltage of the first line, the bias voltage generation section,
A diode-connected first transistor; and a first constant current source connected to the drain terminal of the first transistor, wherein the voltage at the drain terminal of the first transistor is generated as the first bias voltage. Receiving a bias setting voltage for setting a voltage value of the second bias voltage at a gate terminal, and receiving a bias setting voltage at a source terminal from the second constant current source. And a second transistor for receiving the transmitted current, and generating a voltage at the source terminal of the second transistor as the second bias voltage.

In addition, the semiconductor device according to the present invention uses a plurality of display drive voltages obtained by individually amplifying each gradation voltage having a voltage value corresponding to the luminance level of each pixel to a plurality of data lines of the display device. A semiconductor device in which a display driver including a plurality of amplifiers to be supplied is formed,
The display driver includes a bias voltage generation unit that generates a bias voltage, and each of the plurality of amplifiers generates an operation current having a magnitude corresponding to the first and second lines and the bias voltage. A differential that divides the operating current into first and second currents according to a ratio of a voltage value between the grayscale voltage and the display driving voltage and sends them to the first and second lines respectively. A pair and an output unit for generating the display driving voltage based on the voltage of the first line, the bias voltage generating unit receiving a bias setting voltage at its gate terminal, and a voltage at its source terminal Is provided as a bias voltage to each of the plurality of amplifiers.

  In the display driver according to the present invention, when supplying an operating current having a magnitude corresponding to the bias voltage to the differential pair included in the amplifier that supplies the display device with the display drive voltage obtained by amplifying the gradation voltage, the bias voltage A source follower circuit is employed as a bias voltage generation unit for generating. As a result, even when noise occurs in the bias voltage due to a plurality of gradation voltages being simultaneously shifted from a high voltage value (or low voltage value) state to a low voltage value (or high voltage value) state, Since the amount of noise is suppressed by the source follower circuit, it is possible to generate a display drive voltage in which distortion is suppressed.

1 is a block diagram illustrating a configuration of a display device 10 including a display driver according to the present invention. 2 is a block diagram showing an internal configuration of a data driver 13. FIG. 3 is a block diagram illustrating an example of an internal configuration of an output amplifier unit 133. FIG. Is a waveform diagram showing a waveform of a bias voltage VBH2 when the gray voltage B ₁ .about.B _n transitions from the state of simultaneously low voltage value to the state of the high voltage value. It is a circuit diagram which shows the other structure of the 2nd vise voltage generation part. 6 is a block diagram showing another example of the internal configuration of the output amplifier section 133. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a display device 10 including a display driver according to the present invention. As shown in FIG. 1, the display device 10 includes a drive control unit 11, a scan driver 12, a data driver 13, and a display device 20 including a liquid crystal or an organic EL panel.

The display device 20 includes m (m is a natural number of 2 or more) horizontal scanning lines S _{1 to} S _m each extending in the horizontal direction of the two-dimensional screen, and n each extending in the vertical direction of the two-dimensional screen. (N is a natural number of 2 or more) data lines D _{1 to} D _n are formed. Furthermore, display cells PX serving as pixels are formed in the regions of the crossing portions of the horizontal scanning lines and the data lines, that is, the regions surrounded by the broken lines in FIG.

  Based on the input video signal VS, the drive control unit 11 generates a series of pixel data PD representing the luminance level of each pixel by, for example, 6-bit data for each pixel, and a video data signal VD including the series of the pixel data PD. Is supplied to the data driver 13. Further, the drive control unit 11 detects a horizontal synchronization signal from the input video signal VS and supplies it to the scanning driver 12.

The scan driver 12 generates a horizontal scan pulse in synchronization with the horizontal synchronization signal supplied from the drive control unit 11, and sequentially applies it to each of the scan lines S _{1 to} S _m of the display device 20. To do.

  FIG. 2 is a block diagram showing an internal configuration of the data driver 13 as a display driver. The data driver 13 is divided into a single semiconductor chip or a plurality of semiconductor chips.

  As shown in FIG. 2, the data driver 13 includes a data latch unit 131, a gradation voltage conversion unit 132, and an output amplifier unit 133.

The data latch unit 131 sequentially captures a series of pixel data PD included in the video data signal VD supplied from the drive control unit 11. At this time, the data latch unit 131 converts the n pieces of pixel data PD into the pixel data Q _{1 to} Q _{n and} converts the grayscale voltage every time the pixel data PD for one horizontal scanning line (n pieces) is captured. To the unit 132.

The gradation voltage conversion unit 132 converts the pixel data Q _{1 to} Q _n supplied from the data latch unit 131 into gradation voltages B _{1 to} B _n having voltage values corresponding to the luminance levels represented by the pixel data Q. And is supplied to the output amplifier unit 133.

The output amplifier 133 supplies voltages obtained by individually amplifying the grayscale voltages B _{1 to} B _n with a gain of 1 to the data lines D _{1 to} D _n of the display device 20 as display drive voltages G _{1 to} G _n .

FIG. 3 is a block diagram showing an internal configuration of the output amplifier unit 133. As illustrated in FIG. 3, the output amplifier unit 133 includes a bias voltage generation unit BSC and amplifiers AM _{1 to} AM _n .

  The bias voltage generation unit BSC includes a first bias generation circuit including a p-channel MOS (metal oxide semiconductor) transistor P1 and a constant current source MG1, and a second bias circuit including a p-channel MOS transistor P2 and a constant current source MG2. And a bias generation circuit.

The power supply voltage VDD is applied to the source terminal of the transistor P1 of the first bias generation circuit, and its gate terminal and drain terminal are connected to each other. The gate end and drain end of the transistor P1 are connected to one end of the constant current source MG1. That is, the transistor P1 is diode-connected to the constant current source MG1. A ground potential VSS is applied to the other end of the constant current source MG1. The constant current source MG1 flows a predetermined constant current from the drain end of the transistor P1 toward a supply line (not shown) of the ground potential VSS. As a result, a voltage having a constant voltage value is generated at the gate end and the drain end of the transistor P1. The first bias generation circuit supplies the voltage having a constant voltage value to each of the amplifiers AM _{1 to} AM _n as the bias voltage VBH1.

  The constant current source MG2 of the second bias generation circuit receives the supply of the power supply voltage VDD, generates a predetermined constant current, and supplies this to the source terminal of the transistor P2. The ground potential VSS is applied to the drain terminal of the transistor P2, and the bias setting voltage BST is applied to the gate terminal. As a result, a voltage having a voltage value corresponding to the bias setting voltage BST is generated at the source terminal of the transistor P2.

That is, the second bias generation circuit includes a source follower circuit including a transistor P2 and a constant current source MG2, generates a voltage having a voltage value corresponding to the bias setting voltage BST, and uses this as the bias voltage VBH2 to provide the amplifier AM _1. To each of AM _n .

The amplifiers AM _{1 to} AM _n have the same internal configuration. Therefore, the amplifier AM ₁ is extracted below and the internal configuration of each of the amplifiers AM _{1 to} AM _n will be described.

As shown in FIG. 3, each of the amplifiers AM _{1 to} AM _n includes a differential section including p-channel MOS transistors P11 to P14, n-channel MOS transistors N11 and N12, and a p-channel MOS transistor P21. And an output section including an n-channel MOS transistor N21.

  The power supply voltage VDD is applied to the source terminal of the transistor P11 as the first bias transistor, and the bias voltage VBH1 is supplied to the gate terminal. The drain end of the transistor P11 is connected to the source end of the transistor P12. With this configuration, the transistor P11 receives the supply of the power supply voltage VDD, generates a current having a magnitude corresponding to the bias voltage VBH1, and supplies this to the source terminal of the transistor P12.

  A bias voltage VBH2 is supplied to the gate terminal of the transistor P12 as the second bias transistor, and the drain terminal is connected to the source terminals of the transistors P13 and P14 forming a differential pair. With this configuration, the transistor P12 supplies the current supplied from the transistor P12 as an operating current to the source terminals of the transistors P13 and P14 according to the bias voltage VBH2.

The gradation voltage B ₁ is supplied to the gate terminal of the transistor P13, and the drain terminal is connected to the drain terminal of the transistor N11 and the gate terminal of the transistor N21 via the line L1.

The gate terminal of the transistor P14 is connected is supplied with the display driving voltage G ₁ through the output line L0, the drain terminal via the line L2 to the drain of transistor N12. The drain end and the gate end of the transistor N11 are connected to each other, and the gate end is further connected to the gate end of the transistor N11. The ground potential VSS is applied to the source ends of the transistors N11 and N12.

  A power supply voltage VDD is applied to the source terminal of the transistor P21, and a predetermined fixed voltage VT is applied to the gate terminal thereof. The drain end of the transistor P21 is connected to the drain end of the transistor N21 via the output line L0. The ground potential VSS is applied to the source terminal of the transistor N21.

With the configuration shown in FIG. 3, in the amplifier AV ₁ , the transistors P11 and P12 as the operating current generation unit supply an operating current having a magnitude corresponding to the bias voltages VBH1 and VBH2 to the transistors P13 and P14 forming the differential pair. To do. Actually, the transistor P11 generates a current as a source of the operating current, and supplies this to the differential pair (P13, P14) via the transistor P12. The transistor P12 functions as a filter that prevents noise accompanying steep current fluctuations in the differential pair from leaking into the bias voltage VBH1.

Transistor P13 passes a current corresponding to the gradation voltage B ₁ to the line L1. Transistor M2 flows a current corresponding to the display driving voltage G ₁ supplied via the output line L0 to the line L2. That is, the transistor P13 and P14 as differential pair, the operating current supplied from the bias transistor (P11, P12), the first and second ratio of the voltage value of the gray scale voltage B ₁ displays the drive voltage G ₁ The current is divided into two currents, the first current is sent to the line L1, and the second current is sent to the line L2.

With this configuration, the differential section supplies an output voltage drive signal having a level corresponding to the difference value between the gradation voltage B ₁ and the display drive voltage G ₁ to the gate terminal of the transistor N21 of the output section via the line L1. To do. Then, the transistor N21 extracts the output current Io based on the output voltage drive signal from the output line L0. On the other hand, the transistor P21 of the output unit pulls up the voltage of the output line L0 to a voltage value corresponding to the power supply voltage VDD by flowing a current according to the fixed voltage VT to the output line L0. Therefore, the operation of the transistor N21 as described above, the voltage of the output line L0 is decreased by the amount corresponding to the difference value between the gradation voltage B ₁ displays the drive voltage G _1, as a result, equal to the gray scale voltage B ₁ The voltage value is reached. As a result, the display drive voltage G ₁ having a voltage value equal to the gradation voltage B ₁ is output via the output line L0.

In the following, an example is shown in which each of the gradation voltages B _{1 to} B _n simultaneously transitions from the low voltage value V _L state to the high voltage value V _H state at time t0 as shown in FIG. Therefore, an operation performed by the bias voltage generation unit BSC and the amplifiers AM _{1 to} AM _n will be described.

First, when each of the gradation voltages B _{1 to} B _n sharply transitions to the high voltage value V _H as shown in FIG. 4, the voltage value of the node PTAIL in each of the amplifiers AM _{1 to} AM _n is accordingly increased. To increase. As a result, the voltage at the gate end of the transistor P12, that is, the voltage value of the bias voltage VBH2 is temporarily as shown in FIG. 4 due to the parasitic capacitance parasitic between the gate and drain of the transistor P12 connected to the node PTAIL. Increased noise occurs. At this time, if all of the many gradation voltages, for example, gradation voltages B _{1 to} B _n are simultaneously shifted from the low voltage value V _L state to the high voltage value V _H state, the amount of noise increases, and the bias voltage It takes time for the voltage value of VBH2 to return to the original voltage value. During this time, if the voltage value of the bias voltage VBH2 is higher than the predetermined voltage value, the transistor P12 is turned off, and a malfunction occurs in which the operating current temporarily does not flow to the differential pair (P13, P14). ₁ will be distorted.

Therefore, the bias voltage generation unit BSC employs a source follower circuit (P2, MG2) as shown in FIG. 3 as a second bias generation circuit that generates the bias voltage VBH2. In the source follower circuit, the voltage value of the bias voltage VBH2 is if it becomes higher than the voltage value V _R as shown in FIG. 3, for example corresponding to the bias setting voltage BST is following this, the transistor P2 The gate-source voltage decreases. Therefore, at this time, the source-drain current of the transistor P2 becomes large, and the voltage value of the bias voltage VBH2 is lowered. As a result, even if the voltage at the node PTAIL increases temporarily, the transistor P12 as the bias transistor can be maintained in the on state.

Therefore, even when the gradation voltages B _{1 to} B _n are simultaneously shifted from the low voltage value state to the high voltage value state, the above-described malfunction of the temporary stop of the differential unit is avoided. The amplifiers AM _{1 to} AM _n can suppress the influence of noise generated in the bias voltage, and can generate display drive voltages G _{1 to} G _n with reduced waveform distortion.

In the above embodiment, as transistors P1 and P2 of the transistors P11~P14 and the bias voltage generating unit BSC of the differential section of each amplifier AM _{1-Am n,} it adopts the p-channel MOS transistor, n A channel MOS type transistor may be employed. For example, as the second bias generation circuit of the bias voltage generation unit BSC, an n-channel MOS type as shown in FIG. 5 is used instead of the source follower circuit including the p-channel MOS type transistor P2 as shown in FIG. A source follower circuit including the transistor P2a may be employed.

In the configuration shown in FIG. 5, the power supply voltage VDD is applied to the drain terminal of the transistor P2a, and the bias setting voltage BST is supplied to the gate terminal thereof. The source end of the transistor P2a is connected to one end of the constant current source MG2a. The ground potential VSS is applied to the other end of the constant current source MG2a. The constant current source MG2a flows a predetermined constant current toward a supply line (not shown) of the ground potential VSS. Thereby, a voltage having a constant voltage value corresponding to the bias setting voltage BST is generated at the source end of the transistor P2a. The second bias generating circuit is supplied to each of the amplifier AM _{1-Am n} the voltage of the source terminal of the transistor P2a as the bias voltage VBH2.

  The second bias generation circuit shown in FIGS. 3 and 5 employs a source follower circuit including constant current sources (MG2, MG2a), but a source including a resistance element instead of the constant current source. A follower circuit may be adopted.

In the above embodiment, as shown in FIG. 4, the case where all of the gradation voltages B _{1 to} B _n are simultaneously changed from the low voltage value state to the high voltage value state is taken as an example by the bias voltage generation unit BSC. The malfunction avoidance process has been described. However, even when the gradation voltages B _{1 to} B _n are simultaneously shifted from the high voltage value state to the low voltage value state, the above-described malfunction avoidance process is performed in the bias voltage generation unit BSC. . Note that the voltage value of the bias voltage VBH2 is greater than the voltage value corresponding to the bias setting voltage BST, regardless of the number of gradation voltages that simultaneously transition from the low voltage value to the high voltage value or from the high voltage value to the low voltage value state. When the voltage becomes high or low, malfunction avoidance processing by the bias voltage generation unit BSC is similarly performed.

Further, in the example shown in FIG. 3, although the bias voltage generation unit BSC to be provided by one system with respect to the amplifier AM _{1-Am n,} then partition the amplifier AM _{1-Am n} into a plurality of groups, the group You may make it provide the bias voltage generation part BSC separately for every.

For example, as shown in FIG. 6, amplifiers AM _{1 to} AM _n are connected to a first group to which AM _{1 to} AM _k (k is an integer of 2 or more) and a second group to which AM _{k + 1 to} AM _n belong. Divide into groups. Then, the bias voltage generation unit BSCa having the same internal configuration as the bias voltage generation unit BSC shown in FIG. 3 supplies the bias voltages VBH1 and VBH2 to the amplifiers AM _{1 to} AM _k belonging to the first group. Further, the bias voltage generation unit BSCb having the same internal configuration as the bias voltage generation unit BSC shown in FIG. 3 supplies the bias voltages VBH1 and VBH2 to the amplifiers AM _{k + 1 to} AM _n belonging to the second group.

  In the above embodiment, a cascode circuit including the transistor P1 and the constant current source MG1 as shown in FIG. 3 or FIG. 5 is used as the first bias generation circuit of the bias voltage generation unit BSC, and the second bias As the generation circuit, a cascode circuit including a transistor P2 and a constant current source MG2 is employed, but the circuit configuration is not limited to this. That is, if a source follower is employed as the second bias generation circuit, various circuits can be employed for the actual circuit of the source follower and the first bias generation circuit.

In short, the bias voltage generation unit (BSC, BSCa, BSCb) and the plurality of amplifiers (AM _{1 to} AM _n ) included in the output amplifier unit 133 may be anything as long as they have the following configurations. That is, the plurality of amplifiers individually amplify each of the gradation voltages (B _{1 to} B _n ) corresponding to the luminance level of each pixel to generate a plurality of display drive voltages (G _{1 to} G _n ). At this time, each amplifier has an operating current generation unit (P12) that generates an operating current having a magnitude corresponding to the bias voltage (VBH2), and the operating current is determined based on the ratio of the grayscale voltage and the display driving voltage. Display drive based on the differential pair (P13, P14) divided into 1 and second currents and sent to the first line (L1) and the second line (L2), respectively, and the voltage of the first line And an output unit (P21, N21) for generating a voltage. The bias voltage generator (BSC, BSCa, BSCb) receives a bias setting voltage (BST) at its gate terminal, and supplies the voltage at its source terminal as a bias voltage (VBH2) to each of the plurality of amplifiers (P2). ) Including a source follower circuit.

  According to such a configuration, for example, a plurality of gradation voltages rapidly change from a high voltage value (or low voltage value) state to a low voltage value (or high voltage value) state, resulting in a sudden increase in the bias voltage. Even if a significant voltage fluctuation occurs, the source follower circuit can suppress the voltage fluctuation amount. As a result, it is possible to prevent malfunction of the operating current generator that generates the operating current corresponding to the bias voltage, and thus it is possible to generate a display drive voltage with suppressed distortion.

13 Data Driver 20 Display Device 133 Output Amplifier Unit AM _{1 to} AM _n Amplifier BSC Bias Voltage Generation Unit MG1, MG2 Constant Current Sources P1, P2, P11 to P14 Transistors

Claims (10)

A display driver including a plurality of amplifiers for supplying a plurality of display drive voltages obtained by individually amplifying each of gradation voltages having a voltage value corresponding to the luminance level of each pixel to a plurality of data lines of a display device. There,
A bias voltage generation unit for generating a bias voltage;
Each of the plurality of amplifiers is
First and second lines;
An operating current generator that generates an operating current having a magnitude corresponding to the bias voltage;
A differential pair that divides the operating current into first and second currents by a ratio of voltage values of the grayscale voltage and the display driving voltage and sends them to the first and second lines, respectively;
An output unit for generating the display driving voltage based on the voltage of the first line,
The display driver, wherein the bias voltage generation unit includes a source follower circuit including a transistor that receives a bias setting voltage at a gate terminal and supplies a voltage at a source terminal to each of the plurality of amplifiers as the bias voltage. The transistor is a p-channel MOS transistor in which a ground potential is applied to its drain terminal,
The display driver according to claim 1, wherein the source follower circuit includes a constant current source that supplies a predetermined constant current to the source terminal of the transistor. The transistor is an n-channel MOS transistor in which a power supply voltage is applied to its drain terminal,
The display driver according to claim 1, wherein the source follower circuit includes a constant current source that allows a predetermined constant current to flow from a source end of the transistor toward a supply line of a ground potential.   The operating current generator includes a bias transistor that receives the bias voltage at its gate terminal and supplies the operating current having a magnitude corresponding to a voltage value of the bias voltage to the differential pair. The display driver according to claim 1.   5. The display driver according to claim 1, wherein the bias voltage generation unit is individually provided for each group obtained by dividing the plurality of amplifiers into a plurality of groups. A display driver including a plurality of amplifiers for supplying a plurality of display drive voltages obtained by individually amplifying each of gradation voltages having a voltage value corresponding to the luminance level of each pixel to a plurality of data lines of a display device. There,
A bias voltage generator for generating the first and second bias voltages;
Each of the plurality of amplifiers is
A first bias transistor that receives a power supply voltage and generates a current having a magnitude corresponding to the first bias voltage;
A second bias transistor that outputs current generated by the first bias transistor as an operating current in accordance with the second bias voltage;
First and second lines;
A differential pair that divides the operating current into first and second currents by a ratio of voltage values of the grayscale voltage and the display driving voltage and sends them to the first and second lines, respectively;
An output unit for generating the display driving voltage based on the voltage of the first line,
The bias voltage generator is
A diode-connected first transistor; and a first constant current source connected to the drain terminal of the first transistor, wherein the voltage at the drain terminal of the first transistor is generated as the first bias voltage. A first bias voltage generation circuit that
A second constant current source; a second transistor that receives a bias setting voltage that sets a voltage value of the second bias voltage at a gate end; and a current that is sent from the second constant current source at a source end; And a second bias voltage generation circuit that generates a voltage at the source end of the second transistor as the second bias voltage.   7. The display driver according to claim 6, wherein the second transistor is a p-channel MOS transistor in which a ground potential is applied to its drain terminal.   7. The display driver according to claim 6, wherein the second transistor is a p-channel MOS transistor having a power supply voltage applied to its drain terminal.   9. The display driver according to claim 6, wherein the bias voltage generation unit is individually provided for each group obtained by dividing the plurality of amplifiers into a plurality of groups. A display driver including a plurality of amplifiers for supplying a plurality of display drive voltages obtained by individually amplifying each of gradation voltages having a voltage value corresponding to a luminance level of each pixel to a plurality of data lines of a display device A formed semiconductor device comprising:
The display driver includes a bias voltage generation unit that generates a bias voltage;
Each of the plurality of amplifiers is
First and second lines;
An operating current generator that generates an operating current having a magnitude corresponding to the bias voltage;
A differential pair that divides the operating current into first and second currents by a ratio of voltage values of the grayscale voltage and the display driving voltage and sends them to the first and second lines, respectively;
An output unit for generating the display driving voltage based on the voltage of the first line,
The semiconductor device according to claim 1, wherein the bias voltage generation unit includes a source follower circuit including a transistor that receives a bias setting voltage at a gate terminal and supplies a voltage at a source terminal to each of the plurality of amplifiers as the bias voltage.

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