JPH02182018A - Identification circuit - Google Patents

Abstract

PURPOSE:To optimize the input sensitivity of an amplifier and the operating speed of a level discrimination logic section respectively independently by providing a logic level matching circuit converting an output level of an amplifier into a logic level of the level discrimination logic section between the amplifier placed to the prestage and the level discrimination logic section. CONSTITUTION:A logic level matching circuit 5 is placed between an amplifier 2 and a level decision logic section 1 comprising a latch and a flip-flop. The logic decision level matching circuit 6 acts like an attenuator when the output level of the amplifier 2 is larger than the logic level of the level decision logic section 1 and acts like a limiting amplifier when smaller and the output level of the logic level matching circuit 5 is identical to the logic level of a level discrimination logic section 2 of the next stage. Thus, the high performance processing (high sensitivity of the amplifier 2 and fast speed of the level decision logic section 1) of each circuit is attained independently, resulting that the high sensitivity and broad band processing of an identification circuit is attained simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an identification circuit suitable for monolithic integration and capable of highly sensitive broadband operation.

[Conventional technology]

Conventionally, for example, a lunch or a flip-flop has been used as an identification circuit required for a repeater of a pattern transmission system (PCM system, optical transmission system, etc.). In this case, the input sensitivity of the identification circuit is determined by the manual sensitivity of the latch or flip-flop. In order to improve the transmission quality, it is desirable to make the identification probability as small as possible, and for this reason, for example, an identification circuit having a configuration as shown in FIG. 5 is used. That is, in order to achieve high sensitivity, the amplifier 2 is installed at the front stage of the level judgment logic section 1 consisting of a latch or a flip-flop. In this configuration,
The input sensitivity of the discrimination circuit is compared to the input sensitivity of the level judgment logic section 1 consisting of a lunch or a flip-flop.
Since the gain of amplifier 2 is multiplied, high sensitivity can be achieved. Further, in FIG. 5, an output buffer 3 is also added to drive the 50 ohm system at the next stage. Further, in FIG. 5, d is input data, C is a clock, and Q is an identification circuit output signal.

Figure 6 shows an example of a high-frequency wideband identification circuit using npn transistors and series gate circuit technology and having the configuration shown in Figure 5.
Shown in Figure Tag, (b). Figure 6 (a) is from Suzuki et al., “Bipolar Monolithic Multi-Gigabit/Second Determining Circuit,” IE Solid-State Circuits Magazine, 1.
984, 5C-19, pp. 462-467” (M.

5uzukt,et,al,+”A Bipola
r Monolithic Multigi-gabi
t/s Decision C1rcuit”,
IEEE J, 5 solid-state circuit
ts, 1984.5C-19, pp, 462-467
), and Figure 6(b) is “Suzuki et al., “Monolithic 2.1 Gbit/s Decision Circuit with Decision Value Ambiguity Width of Less than 1QmV”, Electronic Engineering Letters, 1985. , Volume 21, Issue 19, 844-8
46 pages” (M.

5uzuki, et, al, , Monolithic
2.1 Gbit/s Decision C1rc
With a Decision Threshold
hold Ambigui-ty Width Of
Less Than l 抛V”, Elec, Let
t, , 1985, Vol. 21. No, 19.1)
I), 844-846).

In Fig. 6 (al, (b)), VCC is the power supply voltage on the high potential side, ■ is the power supply voltage on the low potential side, d is the input data, C is the clock, and Q and ζ are the two-phase output signals of the identification circuit. , V
T is a reference voltage for level determination. Figure 6(a),
(b) In both cases, a differential amplifier is used as the amplifier 2 to achieve high sensitivity, and the level judgment logic section 1 (latch in (a), flip-flop in (b)) is driven differentially and has a low logic amplitude ( In this case, the logical amplitude is 400.500 m
V) to increase speed.

The output buffer 3 uses an oven collector type in FIG. 6(a), and an open emitter type in fbl.

Further, in the figure, a reference voltage generation circuit 4 for a clock and a constant current source is also provided. Both circuit configurations are realized as monolithic ICs using a high-speed St bipolar process, achieving an input sensitivity of 20 mV or less in the high-speed region of several Gb/s.

[Problem to be solved by the invention]

These ICs have the highest performance in terms of both sensitivity and operating speed among those previously reported.
This configuration has the following problems.

In this circuit configuration, in order to achieve even higher sensitivity, it is necessary to increase the gain of amplifier 2. However, since the gain of amplifier 2 becomes thicker, its output level becomes Lunch or flip-flop in the diagram)
If the logic level shifts to a higher or lower potential than the logic level of do. In other words, in this configuration, it is necessary to match the output level of the amplifier 2 with the logic level of the level determination logic section 1, so there is a trade-off between the sensitivity of the amplifier 2 and the operating speed of the level determination logic section 1. There will be off-times, so you cannot have both at their best performance at the same time.

[Means to solve the problem]

In order to solve these problems, the present invention provides a level judgment logic section that measures the output level of the amplifier between a level judgment logic section consisting of a latch or a flip-flop, and an amplifier installed before the level judgment logic section. A logic level matching circuit is provided for converting the logic level into the logic level.

[Effect]

In the identification circuit according to the present invention, there is no trade-off between the sensitivity of the amplifier and the operating speed of the level determination logic section.

〔Example〕

First, the configuration and features of the present invention will be described. The configuration of the present invention is shown in FIG. The configuration shown in FIG. 1 is characterized in that a logic level matching circuit 5 is installed between the amplifier 2 and a level determination logic section 1 consisting of, for example, a lunch or a flip-flop. The logic level matching circuit 5 operates as an attenuator when the output level of the amplifier 2 is larger than the logic level of the level judgment logic section 1, and as a misoring amplifier when it is smaller than the logic level of the logic level matching circuit 5. It is characterized in that the output level is the same as the logic level of the level determination logic section 2 at the next stage.

Next, the differences from the conventional technology will be described. By adding the logic level matching circuit 5, there is no need to consider matching between the output level of the amplifier 2 and the logic level of the level determination logic section l. That is, the trade-off between the sensitivity of the amplifier 2 and the operating speed of the level determination logic section 1 can be eliminated. Therefore, it is possible to independently improve the performance of each circuit (higher sensitivity of the amplifier 2 and faster speed of the level determination logic section 1), and as a result, it is possible to simultaneously achieve higher sensitivity and wider band of the identification circuit.

A first embodiment of the present invention is shown in FIG. 2 (al).
In al, Ql to Q21. Q105. QIO8,
Q109 is a transistor, and QIO1 and QIO2 are diodes. In FIG. 2fa), a latch is used as the level determination logic section 1, but it may of course be a flip-flop. In Figure 2 (al), a differential amplifier 2 with increased gain is used, and an ECL type logic level matching circuit 5 is provided at the subsequent stage.The output level of this matching circuit 5 (
Q6. The emitter potential of Q7) is the same as the logic level of the latch l in the next stage, and in this case, the high level is ■. CVb@
*Low level is Vcc Vbe -400mV (
However, ■1 is the on-voltage between the base and emitter of the transistor). Furthermore, since this ECL type logic level matching circuit 5 also operates as a differential amplifier when its input amplitude is small, the sensitivity of the entire identification circuit is improved accordingly.

FIG. 2 (bl is the second embodiment of the present invention. In the same figure, Q1 to Q21.Q30 to Q41.Q105, Q1
08. Q109 is a transistor, and Q101 and Q102 are diodes. In FIG. 2(b), a full-feedback type amplifier is used as the amplifier 2 to achieve even higher sensitivity.

FIG. 3 shows a comparison of identification sensitivity between the conventional configuration and the embodiment of the present invention. In the figure, the sensitivity mill & ff51 has a conventional configuration (6th
This is the one shown in Figure (a)). In addition, sensitivity curve S2 shows the case where the gain of amplifier 2 is increased in the above conventional configuration, and the sensitivity on the low frequency side increases, but due to the level mismatch between amplifier 2 and level judgment logic section (launch) 1, the sensitivity in the high frequency region increases. It is easy to understand how the performance deteriorates. Sensitivity curve S3 is the result of the first embodiment of the present invention, and its amplifier 2, level judgment logic section 1, etc. are the same as those of sensitivity curve S2, but a logic level matching circuit 5 is newly added. There is. By adding the logic level matching circuit 5, the input level of the level judgment logic section 1 is optimized, and high sensitivity can be achieved by the first stage amplifier 2 without impairing the high speed performance of the level judgment logic section (latch) 1. Compared to conventional characteristics (sensitivity characteristics of curves S1 and S2), both sensitivity and operating speed are approximately twice as high.

Further, the sensitivity curve S4 is the characteristic of the second embodiment, and the sensitivity characteristic is also improved by increasing the sensitivity of the amplifier 2.

Although two embodiments of the present invention have been described above, the present invention is not limited to these.

For example, FIG. 4 fat~(C) shows another embodiment of the present invention (
Examples 3 to 5) are shown below. Figure 4 (
a) is an example in which a cascade type differential amplifier is used as the amplifier 2, and (b) is an example in which a logic level matching circuit 5 is used as the modified (Mo
An example of applying the NTL circuit (defined), and (
C) is a cascade type ECL as the logic level matching circuit 5.
This is an example of applying . In this way, various variations can be considered in the circuit configurations of the amplifier 2 and the logic level matching circuit 5. In addition, in FIG. 4, Q1 to Q14 are transistors, and the transistor Q1 in FIG. 4(a) and (C)
The emitter output signals of transistors Qll and 12 shown in FIG.

〔Effect of the invention〕

As explained above, the present invention provides an arrangement between a level judgment logic section consisting of a latch or a flip-flop and an amplifier installed before the level judgment logic section, so that the output level of the amplifier is adjusted to the logic level of the level judgment logic section. By providing a converting logic level matching circuit, the input sensitivity of the amplifier and the operating speed of the level judgment logic section can be optimized independently, resulting in performance that is more than twice that of the conventional configuration in terms of both input sensitivity and operating frequency. This has the effect of realizing a unique identification circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of the present invention, FIG. 2 is a circuit diagram showing the first and second embodiments of the present invention, FIG. 3 is a performance comparison diagram between the conventional structure and the structure of the present invention, and FIG. FIG. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a block diagram showing the configuration of a conventional identification circuit, and FIG. 6 is a circuit diagram showing an example of a conventional identification circuit. 1...Level judgment logic section, 2...Amplifier, 3...
Output sofa, 4... reference voltage generation circuit, 5... logic level matching circuit.

Claims (1)

[Claims] A logic level matching circuit for converting the output level of the amplifier to the logic level of the level judgment logic section is provided between a level judgment logic section consisting of a latch or a flip-flop and an amplifier installed before the level judgment logic section. An identification circuit characterized by: