JPS63164509A - Delay detecting circuit - Google Patents

Abstract

PURPOSE:To prevent an output from being dropped due to the shift of carrier frequency by delaying a received wave by means of plural circuits having different delay times and selecting and outputting the maximum output out of outputs obtained by detecting the phases of outputs from respective delay circuits. CONSTITUTION:A signal from an input terminal 1 is delayed by a delay line 2 and different phase changes are applied to the delayed signal by plural phase shifters 51-5m. The phase-shifting amounts of the phase shifters 51-5m are changed respectively by phase obtained by dividing 2 equally into (m) sections. The outputs of the plural phase shifters 1-5m are individually detected by phase detectors 31-3m to find out outputs 41-4m and the maximum value out of the outputs 41-4m is selected. Consequently, the detected outputs can be prevented from being dropped due to the shear of carrier frequency or the shear of a delay time difference in the delay lines. The circuit is especially suitable for a high frequency band.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a delay detection circuit, and can be used, for example, in a demodulation circuit in a wireless transmission system using digital phase modulation.

(Prior Art) A conventional method will be explained with reference to FIG. In FIG. 1, 1 is an input terminal, 2 is a delay line, 3 is a phase detector, and 4 is an output terminal. A digital phase modulation signal Vi of 2PSK, 4PSK, etc. (PSK: Phase 5hift Keying) applied to the input terminal 1 is expressed by the following equation.

V1=cos (ωt+θi)
(]) However, i is a code number, and θ indicates the amount of phase modulation corresponding to the modulated signal. Further, ω is the angular frequency of the carrier wave.

(2) If 1 is applied to the phase detector 3 via the delay line 2 having a delay amount τ equal to the code period T, the other input signal of the phase detector 3 becomes the signal VI++ which has been sent by one symbol.

That is, the two signals applied to the phase detector 3 are as follows.

V1=cos(ω(at t+) 10+) (
2a) V1++-CO3 (ω = 10+++)
(2b) Here, the phase detector 3 performs a multiplication operation of the two added signals, so its output is V. 1 is Vo+-V+XV+++=1/2(cos(ωτ+θ,
−θ+++)”cos (2ωt+ωτ+θ□+θi,
l)) (3) Here, the first term ωτ is ωτ−
If we set 2nπ and remove the second term with a low frequency filter, we get
The resulting output V. i' is Vo+'=1/2cosΔθ, where Δθ=01−0I+1, and an output is obtained according to the difference between the phase modulation amounts corresponding to the code numbers i and i+1.

(Problem to be Solved by the Invention) However, in general, the carrier wave frequency ω and the delay time τ of the delay line each have ideal values ω. , τ. There are errors Δω and Δτ from the actual product due to manufacturing variations, temperature changes, etc. In other words, ωmiω. +Δω, τ; τ. +Δτ (5) Therefore, the first term of equation (3) becomes as follows.

]/2cos((ω0+Δω)(τ.+Δτ)+Δθ)
= 1/2 [CO5((ω0+Δω)(τ.+Δτ))
cosΔθ−5jn((ω.+Δω)(τ.1Δτ))
sin Δθ co (6) Here, since the second item is an orthogonal component, if we take only the first item, we get 1/2 cos (ω0τ0+ω0Δτ+Δωτ0÷Δω
Δτ) cos Δθ (7). Here ω. τ, = 2nπ, and if ΔωΔτ〈〈1,'=, 1/2cos(ω0τ0(Δτ/τ.+Δω/
ω. )) cosΔθ (8).

Here, cosΔθ is the output of the phase detector 3 in an ideal state, but in reality, the output decreases due to the previous term including Δω and Δτ. For example, ω. -2π×20G)lz,τo=17
Δω/ω at 2 MHz. −Δτ/? In the case of 0-10-5, it becomes 0.31 times the ideal state (=-10.2 dB), and the output of the phase detector drops significantly.

Viewed from another perspective, this phenomenon is caused by a change in the carrier phase between the input and output terminals of the delay line 2. In the most extreme case, when a phase shift of π/2 occurs, the output of the phase detector 3 is It becomes O.

As described above, when delay detection is performed using the conventional technique, there is a drawback that the demodulated output decreases due to frequency fluctuations of the carrier wave or delay time fluctuations of the delay line. This phenomenon is particularly noticeable in a high frequency band where it is difficult to increase the stability of the carrier frequency, or when a delay line with a relatively low code speed and a large amount of delay is required.

The purpose of the present invention is to solve the problem that the delay detection output of a phase modulated signal decreases due to carrier wave frequency fluctuations or delay line delay time fluctuations, and to provide a delay detection method that is less susceptible to frequency stability or delay line time changes. and to provide its circuits.

(Means for Solving the Problems) The present invention provides a phase detector with a plurality of signals having different phases on a step basis in order to relieve a drop in detection output due to a phase change at the input terminal and output terminal of a delay line. , the maximum detection output is selected from among them.

(Example) Fig. 2 is a diagram explaining the present invention in detail, in which 1 is an input terminal, 2 is a delay line, 3□~3m are phase detectors, 41~4
y is an output terminal, and 51 to 5ffi are phase shifters. Here, phase shifter 5. .about.51 is most suitable when the phase shift amount differs by the phase obtained by dividing 2π into m equal parts. Of course, it doesn't have to be that way. If we add to this the output of the delay line 2 whose carrier wave phase is different between the input terminal and the output terminal, one of the multiple phase shifters 5□~5° will be close to the carrier wave phase of the input terminal of the delay line 2. Contains things. Therefore, the output of the phase detector 3° to which the output of the phase shifter 5° is added can obtain a large value regardless of the carrier phase error between the input terminal and the output terminal of the delay line 2.

FIG. 3 is a diagram illustrating another embodiment of the present invention, 51
°～511. ′ is a phase shifter. This phase shifter 5□゛～5
．． It is preferable that each phase shifter 6' has a phase shift amount obtained by equally dividing 2π by m, and therefore, the outputs of the phase shifters 51' to 5m' are the same as those of the phase shifters 5 and 6' in FIG. The output is similar to ~5o.

FIG. 4 is a diagram illustrating another embodiment of the present invention, 61
~6. n is a delay line. The delay lines 6□ to 6m each have an electrical length of, for example, 1/m wavelength at the carrier frequency, and therefore the phase shifters 51° to 5ffl' in FIG.
The same effect can be obtained.

FIG. 5 is a diagram illustrating another embodiment of the present invention.
~7□ is a delay line. The delay lines 71 to 7, n each have an electrical length difference of one wavelength from one m wavelength at the carrier frequency. Therefore, delay line 7. The output of 7o is equivalent to that of delay lines 61 to 6 in FIG.

FIG. 6 is a diagram illustrating an example of a circuit for selecting the maximum detection output, in which 8a and 8b are input terminals, 9 is an amplitude comparator, and 10
is a switch, and 11 is an output terminal. Input terminals 8a, 8
b shows the phase detector 3 of FIGS. 2, 3, 4, and 5. ~3 out of 3I6. and 3□ outputs are added. Since the amplitude comparator 9 outputs voltages of different polarities depending on the magnitude relationship between the two inputs, if the switch 10 is operated according to the polarity, the larger input signal of the input signals of the input terminals 8a and 8b is outputted to the output terminal 11. can be output to. Circuits similar to this are also connected to the remaining outputs of the phase detectors in Figures 2, 3, 4, and 5, and the outputs of these circuits are used as inputs of similar circuits to successively increase the outputs. By selecting and outputting the input of the phase detector 3. ~3. The largest of n outputs can be selected.

(Effects of the Invention) As explained above, in the differential detection method, multiple signals with different phases are applied to multiple phase detectors in a stepwise manner, and the largest detection output is selected from among them. It is possible to prevent a decrease in the detection output due to a shift in the delay time difference between the delay lines or a shift in the delay time difference between the delay lines.

This effect is particularly noticeable in high frequency bands where it is difficult to increase the stability of the carrier frequency, or in cases where a delay line with a relatively low code rate and a large amount of delay is required.

[Brief explanation of the drawings] The first is a configuration diagram of a conventional delay detection circuit, FIG. 2, FIG.
4 and 5 are block diagrams of the delay detection circuit of the present invention, and FIG. 6 is a diagram illustrating an example of a circuit for selecting the maximum detection output. 1... Input terminal, 2... Delay line, 3... Phase detector, 3,~3... Phase detector, 4... Output terminal,
5I~5 m +++ phase shifter, 6□~6, n-delay line, 7,~7. --Delay line, 8a, 8b--input terminal, 9
...Amplitude comparator, 10-...Switch, 11-...Output terminal.

Claims (4)

[Claims] (1) A plurality of delay variable means having mutually different delay times into which a received wave is input, and a plurality of phase detectors that individually perform phase detection between the output of each of the delay variable means and the received wave. What is claimed is: 1. A delay detection circuit comprising: selecting and outputting the maximum value among the outputs of the plurality of phase shift detectors. (2) The plurality of variable delay means are composed of a single fixed delay means and a plurality of phase shifters connected to this, each having a delay amount different by approximately 2π/m (m is the number of variable delay means). The delay detection circuit according to claim 1, characterized in that: (3) The plurality of variable delay means is a series circuit of a single fixed delay means and m phase shifters connected to the single fixed delay means and having a delay amount of approximately 2π/m (m is the number of variable delay means). A delay detection circuit according to claim 1, characterized in that it is comprised of: (4) The phase shifter having a delay amount of 2π/m is a delay circuit having an electrical length of approximately λ/m (λ is the wavelength) with respect to the carrier frequency. The delayed detection circuit described in Section 3.