JPS6316449U - - Google Patents

Info

Publication number
JPS6316449U
JPS6316449U JP1986110841U JP11084186U JPS6316449U JP S6316449 U JPS6316449 U JP S6316449U JP 1986110841 U JP1986110841 U JP 1986110841U JP 11084186 U JP11084186 U JP 11084186U JP S6316449 U JPS6316449 U JP S6316449U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
external leads
circuit boards
support plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986110841U
Other languages
Japanese (ja)
Other versions
JPH0442936Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986110841U priority Critical patent/JPH0442936Y2/ja
Publication of JPS6316449U publication Critical patent/JPS6316449U/ja
Application granted granted Critical
Publication of JPH0442936Y2 publication Critical patent/JPH0442936Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Casings For Electric Apparatus (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す斜視図、第２図
は本実施例を示す断面図、第３図及び第４図は従
来例を示す断面図である。 １，２…第１及び第２の混成集積回路基板、３
…回路素子、４，５…第１及び第２の外部リード
、６…補強部材、７…枠体、８…突起部、９…支
持板、１０，１１，１２…第１、第２及び第３の
切り欠き部。 FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a sectional view showing this embodiment, and FIGS. 3 and 4 are sectional views showing a conventional example. 1, 2...first and second hybrid integrated circuit boards, 3
...Circuit element, 4, 5...First and second external leads, 6...Reinforcement member, 7...Frame, 8...Protrusion, 9...Support plate, 10, 11, 12...First, second and second 3 notch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路素子が設けられた第１及び第２の混成集積
回路基板と、該第１及び第２の混成集積回路基板
の同一側辺から同一方向に曲折された第１及び第
２の外部リードと、前記第１及び第２の混成集積
回路基板を対向して離間配置する枠体とからなる
混成集積回路において、垂直方向に形成された突
起部と水平方向に形成された支持板とが一体化さ
れた補強部材を前記第１及び第２の外部リード間
に配し、前記第１の外部リードは前記突起部に当
接保持され、前記第１及び第２の外部リードの端
部は前記支持板に設けられた第１及び第２の切り
欠き部内に配置し位置規制することを特徴とする
混成集積回路。 first and second hybrid integrated circuit boards provided with circuit elements; first and second external leads bent in the same direction from the same side of the first and second hybrid integrated circuit boards; In a hybrid integrated circuit comprising a frame body in which the first and second hybrid integrated circuit boards are arranged facing each other and spaced apart from each other, a protrusion formed in a vertical direction and a support plate formed in a horizontal direction are integrated. A reinforcing member is disposed between the first and second external leads, the first external lead is held in contact with the protrusion, and the ends of the first and second external leads are held in contact with the support plate. 1. A hybrid integrated circuit characterized in that the hybrid integrated circuit is disposed within first and second notches provided in the holder and its position is regulated.
JP1986110841U 1986-07-18 1986-07-18 Expired JPH0442936Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986110841U JPH0442936Y2 (en) 1986-07-18 1986-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986110841U JPH0442936Y2 (en) 1986-07-18 1986-07-18

Publications (2)

Publication Number Publication Date
JPS6316449U true JPS6316449U (en) 1988-02-03
JPH0442936Y2 JPH0442936Y2 (en) 1992-10-12

Family

ID=30990216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986110841U Expired JPH0442936Y2 (en) 1986-07-18 1986-07-18

Country Status (1)

Country Link
JP (1) JPH0442936Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013135000A (en) * 2011-12-23 2013-07-08 Denso Corp Power conversion device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013135000A (en) * 2011-12-23 2013-07-08 Denso Corp Power conversion device

Also Published As

Publication number Publication date
JPH0442936Y2 (en) 1992-10-12

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